DE69330646D1 - Datenfliessbandordnungssystem - Google Patents

Datenfliessbandordnungssystem

Info

Publication number
DE69330646D1
DE69330646D1 DE69330646T DE69330646T DE69330646D1 DE 69330646 D1 DE69330646 D1 DE 69330646D1 DE 69330646 T DE69330646 T DE 69330646T DE 69330646 T DE69330646 T DE 69330646T DE 69330646 D1 DE69330646 D1 DE 69330646D1
Authority
DE
Germany
Prior art keywords
data
ordering system
fsm
cpu
requests
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69330646T
Other languages
English (en)
Inventor
V Kabenjian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of DE69330646D1 publication Critical patent/DE69330646D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
DE69330646T 1992-11-25 1993-11-24 Datenfliessbandordnungssystem Expired - Lifetime DE69330646D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US98180692A 1992-11-25 1992-11-25
PCT/US1993/011460 WO1994012935A1 (en) 1992-11-25 1993-11-24 Pipelined data ordering system

Publications (1)

Publication Number Publication Date
DE69330646D1 true DE69330646D1 (de) 2001-09-27

Family

ID=25528665

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69330646T Expired - Lifetime DE69330646D1 (de) 1992-11-25 1993-11-24 Datenfliessbandordnungssystem

Country Status (9)

Country Link
US (2) US5603042A (de)
EP (1) EP0700540B1 (de)
JP (1) JP3425443B2 (de)
KR (1) KR100296517B1 (de)
AT (1) ATE204660T1 (de)
AU (1) AU666999B2 (de)
CA (1) CA2150024C (de)
DE (1) DE69330646D1 (de)
WO (1) WO1994012935A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5638534A (en) * 1995-03-31 1997-06-10 Samsung Electronics Co., Ltd. Memory controller which executes read and write commands out of order
US5666494A (en) * 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
AU9693398A (en) 1997-10-10 1999-05-03 Rambus Incorporated Apparatus and method for pipelined memory operations
EP1327991A3 (de) * 1997-10-10 2005-05-11 Rambus Inc. Vorrichtung und Verfahren für Pipeline-Speicheroperationen
US7325064B2 (en) * 2001-07-17 2008-01-29 International Business Machines Corporation Distributed locking protocol with asynchronous token prefetch and relinquish
US20050144409A1 (en) * 2002-09-11 2005-06-30 Fujitsu Limited Data processing device and method utilizing latency difference between memory blocks
WO2004025478A1 (ja) * 2002-09-11 2004-03-25 Fujitsu Limited メモリブロック間のレイテンシ差を活用するデータ処理装置および方法
US7412574B2 (en) * 2004-02-05 2008-08-12 Micron Technology, Inc. System and method for arbitration of memory responses in a hub-based memory system
JP4982778B2 (ja) * 2008-07-04 2012-07-25 学校法人慶應義塾 電子回路装置
KR102193682B1 (ko) 2014-08-01 2020-12-21 삼성전자주식회사 선택적 ecc 기능을 갖는 반도체 메모리 장치

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4181974A (en) * 1978-01-05 1980-01-01 Honeywell Information Systems, Inc. System providing multiple outstanding information requests
US4661905A (en) * 1983-09-22 1987-04-28 Digital Equipment Corporation Bus-control mechanism
JPS61160142A (ja) * 1984-12-29 1986-07-19 Hitachi Ltd デ−タ処理装置
US4937733A (en) * 1987-05-01 1990-06-26 Digital Equipment Corporation Method and apparatus for assuring adequate access to system resources by processors in a multiprocessor computer system
US4858234A (en) * 1987-09-04 1989-08-15 Digital Equipment Corporation Method and apparatus for error recovery in a multibus computer system
US4864496A (en) * 1987-09-04 1989-09-05 Digital Equipment Corporation Bus adapter module for interconnecting busses in a multibus computer system
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US5239661A (en) * 1989-08-18 1993-08-24 Mitsubishi Denki Kabushiki Kaisha Hierarchical bus circuit having decoder generating local buses and devices select signals enabling switching elements to perform data transfer operations
US5289584A (en) * 1991-06-21 1994-02-22 Compaq Computer Corp. Memory system with FIFO data input
US5471638A (en) * 1991-10-04 1995-11-28 Bull Hn Inforamtion Systems Inc. Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests

Also Published As

Publication number Publication date
US5603042A (en) 1997-02-11
US5737627A (en) 1998-04-07
KR950704742A (ko) 1995-11-20
AU666999B2 (en) 1996-02-29
CA2150024A1 (en) 1994-06-09
EP0700540A4 (de) 1998-06-03
EP0700540B1 (de) 2001-08-22
WO1994012935A1 (en) 1994-06-09
AU5678794A (en) 1994-06-22
CA2150024C (en) 2001-06-12
JP3425443B2 (ja) 2003-07-14
EP0700540A1 (de) 1996-03-13
JPH08503800A (ja) 1996-04-23
ATE204660T1 (de) 2001-09-15
KR100296517B1 (ko) 2001-10-24

Similar Documents

Publication Publication Date Title
KR930001078A (ko) 컴퓨터 시스템
SE9202182D0 (sv) Mirrored memory multi processor system
KR880010365A (ko) 디지탈 데이타 프로세서용 버스 인터페이스 회로
SE8405456D0 (sv) Mycket snabbt minnes- och minnesforvaltningssystem
ATE73241T1 (de) Datenverarbeitungssystembus mit fehlerzyklusbetrieb.
KR970002590A (ko) 집적회로 장치와, 디지탈 데이타 처리 및 비디오 디스플레이 신호 발생 시스템
DE69020569T2 (de) Modulares ein-/ausgabesystem für superrechner.
DE69330646D1 (de) Datenfliessbandordnungssystem
ATE74675T1 (de) Mehrprozessorsteuerung fuer vektorrechner.
HK1053384A1 (en) Data processing apparatus and data input/output method
CA2037491A1 (en) System bus control system in a multi-processor system
DE68926466D1 (de) Integrierte Cachespeichereinheit
NO922092D0 (no) Pc med lokal bussarbitraering
GB1535185A (en) Multiprocessor data processing system peripheral equipment access unit
KR950004022A (ko) 분산처리통합 관리시스템
JPS57113144A (en) Stored program computer
SE9801674D0 (sv) Application specific integrated circuit and transceiver circuit
JPH02108150A (ja) コンピュータの並列分散処理装置
KR930004903B1 (ko) 데이타 버스를 이용한 프로세서간 병렬 데이타 통신시스팀 및 통신방법
SU1735864A1 (ru) Устройство обработки информации
CN113010324A (zh) 一种多核处理器及其控制方法
KR970049517A (ko) 고속 중형컴퓨터에 있어서 isdn보드의 데이타 전달방법
KR960042391A (ko) 고속중형 컴퓨터시스템에 있어서 디엠에이제어기
JPS55122284A (en) Cash memory control unit
KR960018929A (ko) 백플레인버스를 시분할방식으로 사용하기 위한 버스용 모듈

Legal Events

Date Code Title Description
8332 No legal effect for de