SE537101C2 - Halvledarkomponent och förfarande för utformning av en struktur i ett målsubstrat för tillverkning av en halvledarkomponent - Google Patents
Halvledarkomponent och förfarande för utformning av en struktur i ett målsubstrat för tillverkning av en halvledarkomponent Download PDFInfo
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- SE537101C2 SE537101C2 SE1050298A SE1050298A SE537101C2 SE 537101 C2 SE537101 C2 SE 537101C2 SE 1050298 A SE1050298 A SE 1050298A SE 1050298 A SE1050298 A SE 1050298A SE 537101 C2 SE537101 C2 SE 537101C2
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- target substrate
- masking layer
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- etching
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 22
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
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- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- 230000005684 electric field Effects 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
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- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE1050298A SE537101C2 (sv) | 2010-03-30 | 2010-03-30 | Halvledarkomponent och förfarande för utformning av en struktur i ett målsubstrat för tillverkning av en halvledarkomponent |
PCT/EP2011/054850 WO2011120979A1 (en) | 2010-03-30 | 2011-03-29 | Semiconductor device and method of forming a structure in a target substrate for manufacturing a semiconductor device |
KR1020127028454A KR20130030258A (ko) | 2010-03-30 | 2011-03-29 | 반도체 장치 및 반도체 장치의 제조를 위하여 타겟 기판 내에 구조물을 형성하는 방법 |
EP11712516.1A EP2553715B1 (de) | 2010-03-30 | 2011-03-29 | Halbleiterbauelement und verfahren zur formung einer treppenstruktur in einem zielsubstrat zur herstellung eines halbleiterbauelements |
CN2011800266048A CN103026459A (zh) | 2010-03-30 | 2011-03-29 | 半导体装置和在目标基板中形成结构以制造半导体装置的方法 |
US13/629,174 US8748943B2 (en) | 2010-03-30 | 2012-09-27 | Bipolar junction transistor with stair profile |
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SE1050298A SE537101C2 (sv) | 2010-03-30 | 2010-03-30 | Halvledarkomponent och förfarande för utformning av en struktur i ett målsubstrat för tillverkning av en halvledarkomponent |
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SE1050298A1 SE1050298A1 (sv) | 2011-10-01 |
SE537101C2 true SE537101C2 (sv) | 2015-01-07 |
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SE1050298A SE537101C2 (sv) | 2010-03-30 | 2010-03-30 | Halvledarkomponent och förfarande för utformning av en struktur i ett målsubstrat för tillverkning av en halvledarkomponent |
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US (1) | US8748943B2 (de) |
EP (1) | EP2553715B1 (de) |
KR (1) | KR20130030258A (de) |
CN (1) | CN103026459A (de) |
SE (1) | SE537101C2 (de) |
WO (1) | WO2011120979A1 (de) |
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US9337268B2 (en) * | 2011-05-16 | 2016-05-10 | Cree, Inc. | SiC devices with high blocking voltage terminated by a negative bevel |
US9349797B2 (en) | 2011-05-16 | 2016-05-24 | Cree, Inc. | SiC devices with high blocking voltage terminated by a negative bevel |
EP2761660B1 (de) | 2012-01-18 | 2017-09-27 | Fairchild Semiconductor Corporation | Bipolartransistor mit abstandhalterschicht und herstellungsverfahren dafür |
JP6335795B2 (ja) | 2012-02-06 | 2018-05-30 | クリー インコーポレイテッドCree Inc. | 負ベベルにより終端した、高い阻止電圧を有するSiC素子 |
US9240359B2 (en) | 2013-07-08 | 2016-01-19 | Applied Materials, Inc. | 3D NAND staircase CD control by using interferometric endpoint detection |
JP2015032665A (ja) * | 2013-08-01 | 2015-02-16 | 住友電気工業株式会社 | ワイドバンドギャップ半導体装置 |
US9425265B2 (en) | 2013-08-16 | 2016-08-23 | Cree, Inc. | Edge termination technique for high voltage power devices having a negative feature for an improved edge termination structure |
US9601348B2 (en) * | 2014-03-13 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method of forming same |
US9299580B2 (en) | 2014-08-19 | 2016-03-29 | Applied Materials, Inc. | High aspect ratio plasma etch for 3D NAND semiconductor applications |
EP3222759A4 (de) * | 2014-11-18 | 2018-05-30 | Kwansei Gakuin Educational Foundation | Oberflächenbehandlungsverfahren für sic-substrat |
US9496250B2 (en) * | 2014-12-08 | 2016-11-15 | Globalfoundries Inc. | Tunable scaling of current gain in bipolar junction transistors |
US20220165888A1 (en) * | 2018-10-09 | 2022-05-26 | National Technology & Engineering Solutions Of Sandia, Llc | High Voltage Gallium Nitride Vertical PN Diode |
US12087572B2 (en) * | 2019-03-28 | 2024-09-10 | Lam Research Corporation | Etch stop layer |
CN111029373A (zh) * | 2019-11-18 | 2020-04-17 | 武汉华星光电半导体显示技术有限公司 | 显示面板及其制备方法 |
CN113161236A (zh) * | 2021-03-12 | 2021-07-23 | 武汉高芯科技有限公司 | 一种薄膜刻蚀方法 |
CN114334621B (zh) * | 2022-01-04 | 2023-08-11 | 广东芯粤能半导体有限公司 | 半导体结构、半导体器件及其制备方法 |
US20240006491A1 (en) * | 2022-06-29 | 2024-01-04 | Globalfoundries U.S. Inc. | Bipolar transistor with stepped emitter |
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US3878008A (en) | 1974-02-25 | 1975-04-15 | Us Navy | Method of forming high reliability mesa diode |
DE3879471T2 (de) * | 1988-04-21 | 1993-09-16 | Ibm | Verfahren zur herstellung eines photoresistmusters und apparat dafuer. |
US4957875A (en) * | 1988-08-01 | 1990-09-18 | International Business Machines Corporation | Vertical bipolar transistor |
US5236547A (en) * | 1990-09-25 | 1993-08-17 | Kabushiki Kaisha Toshiba | Method of forming a pattern in semiconductor device manufacturing process |
US5281500A (en) * | 1991-09-04 | 1994-01-25 | Micron Technology, Inc. | Method of preventing null formation in phase shifted photomasks |
US5967795A (en) * | 1995-08-30 | 1999-10-19 | Asea Brown Boveri Ab | SiC semiconductor device comprising a pn junction with a voltage absorbing edge |
JP2001510636A (ja) | 1997-02-03 | 2001-07-31 | ザ ウィタカー コーポレーション | ヘテロジャンクションバイポーラトランジスタにおける不動化棚を製造する自己整合方法 |
US5895269A (en) | 1997-12-18 | 1999-04-20 | Advanced Micro Devices, Inc. | Methods for preventing deleterious punch-through during local interconnect formation |
US6562251B1 (en) | 2000-07-26 | 2003-05-13 | Aiwa Co., Ltd. | Chemical-mechanical contouring (CMC) method for forming a contoured surface using a stair-step etch |
JP2008192857A (ja) | 2007-02-05 | 2008-08-21 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
SE532625C2 (sv) * | 2007-04-11 | 2010-03-09 | Transic Ab | Halvledarkomponent i kiselkarbid |
TW200843105A (en) | 2007-04-25 | 2008-11-01 | Promos Technologies Inc | Vertical transistor and method for preparing the same |
US8652763B2 (en) | 2007-07-16 | 2014-02-18 | The Board Of Trustees Of The University Of Illinois | Method for fabricating dual damascene profiles using sub pixel-voting lithography and devices made by same |
JP5372002B2 (ja) | 2007-11-09 | 2013-12-18 | クリー インコーポレイテッド | メサ構造とメサ段差を含むバッファ層とを備えた電力半導体デバイス |
JP5377940B2 (ja) | 2007-12-03 | 2013-12-25 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US8003522B2 (en) * | 2007-12-19 | 2011-08-23 | Fairchild Semiconductor Corporation | Method for forming trenches with wide upper portion and narrow lower portion |
US7759186B2 (en) * | 2008-09-03 | 2010-07-20 | The United States Of America As Represented By The Secretary Of The Navy | Method for fabricating junction termination extension with formation of photosensitive dopant mask to control doping profile and lateral width for high-voltage electronic devices |
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SE1050298A1 (sv) | 2011-10-01 |
US8748943B2 (en) | 2014-06-10 |
KR20130030258A (ko) | 2013-03-26 |
US20130020611A1 (en) | 2013-01-24 |
CN103026459A (zh) | 2013-04-03 |
EP2553715A1 (de) | 2013-02-06 |
WO2011120979A1 (en) | 2011-10-06 |
EP2553715B1 (de) | 2015-07-15 |
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