JP2022503888A - 広バンド・ギャップ半導体デバイスを製造するときの高エネルギ注入中におけるマスキング・システムおよび方法 - Google Patents
広バンド・ギャップ半導体デバイスを製造するときの高エネルギ注入中におけるマスキング・システムおよび方法 Download PDFInfo
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- 239000007924 injection Substances 0.000 title claims abstract description 161
- 238000002347 injection Methods 0.000 title claims abstract description 161
- 238000000034 method Methods 0.000 title claims abstract description 133
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 230000000873 masking effect Effects 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title description 21
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 121
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 111
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 40
- 229920005591 polysilicon Polymers 0.000 claims description 40
- 150000002500 ions Chemical class 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000005304 joining Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 25
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000002184 metal Substances 0.000 description 18
- 239000002019 doping agent Substances 0.000 description 16
- 230000036961 partial effect Effects 0.000 description 14
- 235000012431 wafers Nutrition 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 238000013461 design Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000010884 ion-beam technique Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000000708 deep reactive-ion etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 230000007123 defense Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000011368 organic material Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- XGVXKJKTISMIOW-ZDUSSCGKSA-N simurosertib Chemical compound N1N=CC(C=2SC=3C(=O)NC(=NC=3C=2)[C@H]2N3CCC(CC3)C2)=C1C XGVXKJKTISMIOW-ZDUSSCGKSA-N 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000012899 standard injection Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
【選択図】図3
Description
Claims (26)
- 中間半導体デバイス構造体であって、
第1導電型を有するSiC基板層と、
前記SiC基板層上に配置され、前記第1導電型を有する、炭化硅素(SiC)エピタキシャル(エピ)層と、
前記SiCエピ層の第1部分上に直接配置され、5マイクロメートル(μm)と20μmとの間の厚さを有するシリコン高エネルギ注入マスク(SiHEIM)であって、500キロ電子ボルト(keV)よりも高い注入エネルギを有する高エネルギ注入プロセス中に、前記SiCエピ層の第1部分の注入を阻止するように構成される、SiHEIMと、
を備える、中間半導体デバイス構造体。 - 請求項1記載の中間デバイス構造体において、前記高エネルギ注入プロセスの注入エネルギが、10メガ電子ボルト(MeV)と50MeVとの間であり、前記SiHEIMが、前記高エネルギ注入プロセス中における前記第1導電型のイオンまたは第2導電型のイオンの注入を阻止するように構成される、中間デバイス構造体。
- 請求項1記載の中間デバイス構造体において、前記SiHEIMが、前記SiCエピ層の第2部分の上方に直接定められたトレンチ構造を含み、前記トレンチ構造が、前記高エネルギ注入プロセス中における注入に、前記SiCエピ層の第2部分を露出させるように構成される、中間デバイス構造体。
- 請求項3記載の中間デバイス構造体において、前記トレンチ構造が、1μmと20μmとの間のそれぞれのトレンチ深さと、1μmと10μmとの間のそれぞれのトレンチ幅と、1:2と1:20との間のアスペクト比とを有する、中間デバイス構造体。
- 請求項3記載の中間デバイス構造体において、前記SiCエピ層の第1部分が、前記SiCエピ層の第2部分に隣接して配置され前記第1導電型を有する高エネルギ注入領域を含み、前記SiHEIMが、前記高エネルギ注入プロセス中における前記SiCエピ層の第2部分の第2導電型のイオンの注入を選択的に許容するように構成される、中間デバイス構造体。
- 請求項1記載の中間デバイス構造体において、前記SiHEIMが、立法センチメートル(cm3)あたり1×1016と立方センチメートル(cm3)あたり1×1020との間のドーピングを有し、導電性であり、前記SiHEIMが、前記高エネルギ注入プロセス中における前記中間デバイス構造体の荷電を阻止するように構成される、中間デバイス構造体。
- 請求項1記載の中間デバイス構造体において、前記SiHEIMが本質的にシリコンで構成される、中間デバイス構造体。
- 請求項1記載の中間デバイス構造体において、前記SiHEIMが、パターニングされた酸化物層上に直接配置されパターニングされたポリシリコン層を含み、一方、前記酸化物層が、前記SiCエピ層の第1部分上に直接配置される、中間デバイス構造体。
- 方法であって、
SiC半導体層上に炭化硅素(SiC)エピタキシャル(エピ)層を形成するステップと、
前記SiCエピ層上にポリシリコン・マスク層を配置するステップと、
前記ポリシリコン・マスク層をパターニングして、前記SiCエピ層の第1部分上に高エネルギ注入シリコン・マスク(SiHEIM)を直接生成するステップと、
前記SiC層の高エネルギ注入を実行して、前記SiCエピ層内に高エネルギ注入領域を形成するステップであって、前記高エネルギ注入領域が、5マイクロメートル(μm)と10μmとの間の深さを有する、ステップと、
を含む、方法。 - 請求項9記載の方法において、高エネルギ注入を実行するステップが、前記高エネルギ注入の間、前記SiC層を加熱するステップを含む、方法。
- 請求項9記載の方法において、前記SiCエピ層上に前記ポリシリコン・マスク層を配置するステップが、
マスキング・ウェハの酸化物層を平面化するステップであって、前記マスキング・ウェハが、前記ポリシリコン・マスク層上に直接配置された平面化酸化物層を含み、前記ポリシリコン・マスク層が、埋め込み酸化物(BOX)層上に直接配置され、前記埋め込み酸化物層(BOX)層が、シリコン・ハンドル・ウェハ上に直接配置される、ステップと、
前記マスキング・ウェハの平面化酸化物層を、前記SiCエピ層に接合するステップと、
前記シリコン・ハンドル・ウェハと前記マスキング・ウェハのBOX層とを除去して、前記平面化酸化物層上に直接配置された前記ポリシリコン・マスク層を生成するステップと、
を含む、方法。 - 請求項9記載の方法において、前記ポリシリコン・マスク層をパターニングするステップが、
フォトレジスト層を前記ポリシリコン・マスク層上に直接配置するステップと、
フォトリソグラフィを実行して前記フォトレジスト層をパターニングし、フォトレジスト・マスクを生成するステップと、
前記SiCエピ層の第2部分からフォトレジスト・マスクによって露出された前記ポリシリコン・マスク層の部分をエッチングして、前記ポリシリコン・マスク層を前記SiHEIMにパターニングするステップと、
を含む、方法。 - 請求項12記載の方法において、前記SiHEIMが、前記SiCエピ層上に直接配置された酸化物層を含み、前記ポリシリコン・マスク層が、前記酸化物層上に直接配置され、前記エッチングするステップが、前記フォトレジスト・マスクによって露出された前記ポリシリコン・マスク層の部分、および前記ポリシリコン・マスク層の下にある前記酸化物層の部分をエッチングして、前記ポリシリコン・マスク層を前記SiHEIMにパターニングするステップを含む、方法。
- 請求項9記載の方法において、前記高エネルギ注入領域が、立法センチメートル(cm3)あたり約1×1014以上のドーピング濃度を含む、方法。
- 請求項9記載の方法において、前記高エネルギ注入領域が、立方センチメートル(cm3)あたり約5×1015と立方センチメートル(cm3)あたり約1×1017との間のドーピング濃度を含む、方法。
- 請求項9記載の方法であって、デバイス層を形成するステップを含み、前記デバイスが、金属酸化物半導体電界効果トランジスタ(MOSFET)、接合型電界効果トランジスタ(JFET)、バイポーラ接合型トランジスタ(BJT)、またはダイオードを含む、方法。
- 中間半導体デバイス構造体であって、
第1導電型を有するSiC基板層と、
前記SiC基板層上に配置され、前記第1導電型を有する炭化硅素(SiC)エピタキシャル(エピ)層と、
前記SiCエピ層の第1部分上に直接配置されたシリコン高エネルギ注入マスク(SiHEIM)と、
前記SiHEIMによって露出された前記SiCエピ層の第2部分に配置され、第2導電型を有する高エネルギ注入領域であって、2μmと15μmとの間の深さを有する、高エネルギ注入領域と、
を備える、中間半導体デバイス構造体。 - 請求項17記載の中間デバイス構造体において、前記高エネルギ注入領域が、5μmと10μmとの間の深さを有する、中間デバイス構造体。
- 請求項17記載の中間デバイス構造体において、前記SiHEIMが、前記SiCエピ層の第2部分を露出する前記SiCエピ層の第2部分の上方に直接定められた複数のトレンチ構造を含み、前記複数のトレンチ構造の各々が、前記SiCエピ層の上面に対して垂直なそれぞれの側壁を含む、中間デバイス構造体。
- 請求項16記載の中間デバイス構造体において、前記複数のトレンチ構造の各々が、1μmと20μmとの間のそれぞれのトレンチ深さを有する、中間デバイス構造体。
- 請求項16記載の中間デバイス構造体において、前記複数のトレンチ構造の各々が、1μmと10μmとの間であるそれぞれのトレンチ幅を有する、中間デバイス構造体。
- 請求項17記載の中間デバイス構造体において、前記高エネルギ注入領域が、前記SiCエピ層の上面に対して垂直に定められたエッジを含む、中間デバイス構造体。
- 請求項17記載の中間デバイス構造体において、前記SiCエピ層が、荷電平衡(CB)またはスーパージャンクション(SJ)層であり、前記SiCエピ層の第1部分が、前記第1高エネルギ注入領域に隣接して配置され、前記第1導電型を有する第2高エネルギ注入領域を含む、中間デバイス構造体。
- 請求項17記載の中間デバイス構造体において、前記半導体デバイスが、前記SiC基板層上に配置され前記SiCエピ層を含む複数のSiCエピ層を備え、前記高エネルギ注入領域が、前記複数のSiCエピ層の各々に少なくとも部分的に配置される、中間デバイス構造体。
- 請求項17記載の中間デバイス構造体において、前記高エネルギ注入領域が、前記SiCエピ層の上面から、前記SiCエピ層の厚さ全体を貫通する、中間デバイス構造体。
- 請求項17記載の中間デバイス構造体において、前記SiHEIMが、前記高エネルギ注入領域を形成した高エネルギ注入プロセスの結果として前記第2導電型を有する、中間デバイス構造体。
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