WO2023169592A1 - Mosfet器件及其制造方法 - Google Patents

Mosfet器件及其制造方法 Download PDF

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Publication number
WO2023169592A1
WO2023169592A1 PCT/CN2023/082486 CN2023082486W WO2023169592A1 WO 2023169592 A1 WO2023169592 A1 WO 2023169592A1 CN 2023082486 W CN2023082486 W CN 2023082486W WO 2023169592 A1 WO2023169592 A1 WO 2023169592A1
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region
ions
implantation
substrate
layer
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PCT/CN2023/082486
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English (en)
French (fr)
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李翔
谢志平
丛茂杰
梁新颖
张渝剀
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中芯越州集成电路制造(绍兴)有限公司
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Priority to JP2023546028A priority Critical patent/JP2024512868A/ja
Priority to EP23741247.3A priority patent/EP4270490A1/en
Publication of WO2023169592A1 publication Critical patent/WO2023169592A1/zh

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Definitions

  • the present invention relates to the technical field of MOSFET device manufacturing, and in particular to a MOSFET device and a manufacturing method thereof.
  • Silicon carbide (SiC) MOSFET Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor
  • SiC Silicon carbide
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor
  • Al (aluminum) ion implantation has weak diffusion in SiC, in the existing planar gate SiC MOSFET process, it is usually first through multiple Al ion implantations to obtain a P well of a certain depth, and then through ion implantation in the P well N+ source area, P+ body area (also called P+ contact area), etc. are formed in it.
  • the purpose of the present invention is to provide a MOSFET device and a manufacturing method thereof, which can avoid damage to the P-well channel surface by ion injection, so as to achieve high conduction performance of the device.
  • the present invention provides a manufacturing method of a MOSFET device, which includes the following steps:
  • first well ions of a first conductivity type into a front surface layer of the substrate to form a first implantation region
  • the first well ions in the first implantation region are activated so that the junction of the first implantation region diffuses to a required width laterally and connects with the second implantation region longitudinally to form the required well region;
  • a sequentially stacked gate oxide layer and a gate electrode are formed on the front surface of the substrate, and a region in contact between the first injection region and the gate oxide layer serves as a channel of the MOSFET device.
  • a patterned mask layer for defining a well region is also formed on the front surface of the substrate; thereafter, using the pattern
  • the mask layer is used as a mask, and the first well ions, the second well ions and the source ions are sequentially implanted into the substrate.
  • the method further includes:
  • the first trap ions include boron ions or boron fluoride ions; the second trap ions include aluminum ions.
  • the implantation process parameters of the first trap ions include: the implantation energy is 50keV-300keV, and the implantation dose is 1E11/cm 2 -6E14/cm 2 .
  • the first trap ions in the first implantation region are activated through an annealing process, the annealing temperature is 1500°C to 1900°C, and the annealing time is 2min to 200min.
  • the substrate includes a silicon carbide layer of a second conductivity type, and the first implantation region and the second implantation region are both formed in the silicon carbide layer.
  • the manufacturing method also includes:
  • interlayer dielectric layer forming an interlayer dielectric layer on the front surface of the substrate, the interlayer dielectric layer burying the gate electrode and exposing part of the source region;
  • a drain metal layer is formed on the back side of the substrate.
  • the present invention also provides a MOSFET device, which includes:
  • first conductive type well region including a first implantation region and a second implantation region formed from top to bottom, the first implantation region being formed in the surface layer of a partial region of the front surface of the substrate, The second implantation region is formed in the substrate below the bottom of the first implantation region, and the first implantation region is diffused in the longitudinal direction to contact the second implantation region;
  • a gate oxide layer and a gate electrode are sequentially stacked on the front surface of the substrate, and the gate electrode is in contact with both the first injection region and the source region.
  • the first injection region is laterally opposite to the
  • the second implanted region extends further at the bottom of the gate.
  • the substrate includes a silicon carbide layer of a second conductivity type, the first implantation region and the second implantation region are both formed in the silicon carbide layer; the first implantation region is doped
  • the first conductive type ions include boron ions or boron fluoride ions; the first conductive type ions doped in the second implantation region include aluminum ions
  • the technical solution of the present invention has at least one of the following beneficial effects:
  • the same mask layer can be used for ion implantation in the first implantation area, the second implantation area and the source area.
  • the process is simple to implement and can effectively reduce the number of photolithography times.
  • FIG. 1 is a schematic flow chart of a manufacturing method of a MOSFET device according to an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of the device structure in the manufacturing method of the MOSFET device shown in FIG. 1 .
  • first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the invention.
  • Spatial relational terms such as “under”, “under”, “under”, “on”, “above”, “above”, etc. may be used here for convenience of description This describes the relationship of one element or feature to other elements or features illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as “below,””under,” or “beneath” would then be oriented “above” the other elements or features.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
  • the singular forms "a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly dictates otherwise.
  • the term “comprising” is used to identify the presence of possible features, steps, operations, elements and/or components, but does not exclude the presence of one or more other features, steps, operations, elements, components and/or groups or Add to.
  • the term “and/or” includes any and all combinations of the associated listed items.
  • An embodiment of the present invention provides a method for manufacturing a MOSFET device, which includes the following steps:
  • S1 provide a substrate, and inject first well ions of a first conductivity type (for example, P type) into the front surface layer of the substrate to form a first implantation region;
  • a first conductivity type for example, P type
  • S3 Implant source ions of a second conductivity type (for example, N type) into the surface layer of the first implantation region to form a source region;
  • a second conductivity type for example, N type
  • S5 Form a sequentially stacked gate oxide layer and a gate electrode on the front surface of the substrate, and the area in contact between the first injection region and the gate oxide layer serves as the channel of the MOSFET device.
  • any suitable semiconductor material such as silicon carbide and silicon may be provided to form the substrate 100 .
  • the provided substrate 100 is an N-type silicon carbide substrate, and has three layers from bottom to top, namely an N+ substrate 100a, a buffer layer 100b and an N-drift layer 100c.
  • the N-drift layer 100c contains N-type ions. The doping concentration is lower than that of N-type ions in the N+ substrate 100a.
  • step S1 first, the surface of the substrate 100 can be cleaned and dried; then, the mask layer material is deposited on the N-drift layer 100c, and optionally
  • the mask layer material is deposited on the N-drift layer 100c, and optionally
  • one or more of polycrystalline silicon (poly Si), monocrystalline silicon (Si), silicon dioxide (SiO 2 ), silicon nitride (SiN), etc. can be a single layer film or a variety of different films.
  • the film of the material is superimposed, and the mask layer material is photolithographically and etched to form a patterned mask layer 200 for defining the P-well to be formed.
  • P-well injection windows (not shown) to be formed are defined on both sides of the patterned mask layer 200; then, using the patterned mask layer 200 as a mask, the N-drift layer 100c is P-type first well ions are implanted into the surface layer to form the first implantation region 101 in the surface layer of the N-drift layer 100c on both sides of the patterned mask layer 200.
  • the first well ions selected in this step can be in the N-drift layer 100c Ions that form holes and can diffuse more easily at high temperatures than subsequent second well ions and source ions.
  • the first well ions are boron ions or boron fluoride ions
  • the implantation direction can be perpendicular to the surface of the N-drift layer 100c
  • the implantation energy is 50keV ⁇ 300keV (such as 100keV, 200keV, etc.)
  • the implantation dose is 1E11 /cm 2 ⁇ 6E14/cm 2 (such as 5E12/cm 2 , 1E13/cm 2 , etc.).
  • step S2 the patterned mask layer 200 is used as a mask to implant P-type second well ions into the N-drift layer 100c below the first implantation region 101 to
  • the second implantation region 102 is formed in the N-drift layer 100c below the first implantation region 101 on both sides of the patterned mask layer 200, whereby the second implantation region 102 can form a deeper junction than the first implantation region 101.
  • the N-drift layer 100c under the first implantation region 101 can be ion-implanted vertically or obliquely through multiple aluminum (Al) ion implantations.
  • the temperature is 400°C ⁇ 1000°C (such as 500°C, 800°C, etc.)
  • the injection energy is 200keV ⁇ 500keV (such as 300keV, 400keV, etc.)
  • the injection dose is 1E11/cm 2 ⁇ 6E14/cm 2 (such as 5E12/cm 2 , 1E13/cm 2 , 1E14/cm 2 , etc.).
  • step S3 the patterned mask layer 200 is used as a mask, and the surface layer of the first injection region 101 is vertically or obliquely adjusted according to the depth requirements and width requirements of the source region design.
  • N-type source ions are implanted to form source regions 103 in the surface layer of the first implantation region 101 on both sides of the patterned mask layer 200 .
  • N-type source ions include at least one of phosphorus (P) ions, arsenic (As) ions, nitrogen (N) ions, etc.
  • the injection energy is 50keV ⁇ 300keV (such as 100keV, 200keV, etc.)
  • the injection dose is 1E14/cm 2 ⁇ 1E16/cm 2 (such as 5E14/cm 2 , 1E15/cm 2 , 5E15/cm 2 , etc.).
  • step S3 optionally, after forming the source region 103, the patterned mask layer 200 is removed, and P-type body region ions are implanted in part of the source region 103.
  • a body region 104 also called a contact region
  • the bottom of the body region 104 penetrates into part of the first implantation region 101 to short-circuit the source region 103 and the first implantation region 101, and its doping concentration of P-type ions is high. in the first injection region 101.
  • the body region ions may include at least one of boron ions, boron fluoride ions and aluminum ions, the implantation energy is 50keV-300keV (such as 100keV, 200keV, etc.), and the implantation dose is 1E14/cm 2 -1E16 /cm 2 (such as 5E14/cm 2 , 1E15/cm 2 , 5E15/cm 2 , etc.).
  • step S4 the substrate 100 is subjected to a high-temperature annealing process.
  • the temperature is 1500°C ⁇ 1900°C (such as 1650°C, 1700°C, 1800°C, etc.), and the annealing time is 2min ⁇ 200min (such as 10min, 20min, 50min, 100min, etc.).
  • the high-temperature annealing process causes the first well ions such as boron ions in the first implantation region 101 to diffuse.
  • the bottom of the diffused first implantation region 101' is vertically connected to the top of the second implantation region 102, and laterally extends to The required width of the P-well to subsequently provide the required channel width.
  • the diffusion of the second well ions in the second implantation region 102 and the P-type ions in the N-type ion body region 104 in the source region 103 is weaker than that of the first well ions in the first implantation region 101.
  • the N-drift layer 101c between the diffused first implanted regions 101' serves as a depletion region.
  • the required well region is composed of the upper diffused first implantation region 101' and the lower second implantation region 102, and since the required channel is formed by diffusion through the first implantation region 101, The channel surface can be greatly reduced in roughness, which in turn can reduce the interface scattering of channel electrons in the final MOSFET device, thereby improving its channel mobility.
  • step S5 first, a suitable gate oxide process such as thermal oxidation process or chemical vapor deposition can be used to perform the process on the body region 104, the source region 103, and the diffused first implantation region 101. ' and a gate oxide layer 301 is formed on the front surface of the N-drift layer 100c; then a gate material layer can be deposited on the surface of the gate oxide layer 301, and the deposited gate material layer and gate oxide layer 301 can be photolithographed and etched The gate electrode 302 is formed by etching. The formed gate 302 overlaps with both the diffused first implant region 101' and the source region 104, and the area where the diffused first implant region 101' contacts the gate oxide layer 301 serves as the channel of the MOSFET device.
  • a suitable gate oxide process such as thermal oxidation process or chemical vapor deposition can be used to perform the process on the body region 104, the source region 103, and the diffused first implantation region 101.
  • a gate oxide layer 301 is formed on the
  • step S4 since the P well is formed by diffusion in step S4, roughness of the channel surface can be effectively avoided, and the SiC crystal quality of the N-drift layer 100c used as the depletion region can also be ensured to be intact. Therefore, the formed The quality of the gate oxide layer 301 reduces the channel defect density, further improves the temperature drift performance of the device, and further improves the reliability of the device.
  • the gate electrode 302 covers the front surface of the substrate 100 with an interlayer dielectric layer 400 through a chemical vapor deposition process or the like.
  • the interlayer dielectric layer 400 may be a single-layer dielectric film structure, or may be It is a structure composed of multiple layers of dielectric films.
  • photolithography and etching are performed on the interlayer dielectric layer 400 to pattern the interlayer dielectric layer 400.
  • the patterned interlayer dielectric layer 400 can be The gate electrode 302 is buried and part of the source region 103 is exposed.
  • a source metal layer 500 (for example, a metal material or alloy such as copper, aluminum, gold, etc.) is formed on the interlayer dielectric layer 400 through a suitable process such as metal sputtering deposition or evaporation.
  • the source metal layer 500 is electrically connected to both the source region 103 and the body region 104.
  • a drain metal layer (not shown) is formed on the back surface of the N+ substrate 100a.
  • the manufacturing method of the MOSFET device in this embodiment forms the required well region through diffusion.
  • the channel surface can be greatly reduced in roughness and interface scattering of channel electrons, thereby improving the channel mobility.
  • the channel surface can be greatly reduced and the interface scattering of channel electrons can be reduced.
  • it can improve the channel defect energy level and gate oxide quality, further improve the temperature drift performance of the device, and further improve the reliability of the device.
  • the ion implantation of the first implantation region, the second implantation region and the source region can be implemented using the same patterned mask layer 200, which makes the process simple to implement and can effectively reduce the number of photolithography times.
  • An embodiment of the present invention also provides a MOSFET device, which is preferably manufactured using the manufacturing method of the MOSFET device of the present invention.
  • the MOSFET device includes:
  • Substrate 100 which may be any suitable semiconductor material.
  • the substrate 100 is an N-type silicon carbide substrate, and has three layers from bottom to top, namely the N+ substrate 100a, the buffer layer 100b and the N-drift layer 100c;
  • a well region of a first conductivity type (for example, P type).
  • the well region includes a first injection region 101 and a second injection region 102 formed from top to bottom.
  • the first injection region 101 is formed on the front side of the N-drift layer 100c.
  • the second injection region 102 is formed in the N-drift layer 100c below the bottom of the first injection region 101, and the first injection region 101 diffuses in the longitudinal direction to connect with the second injection region 102; the first injection region
  • the first conductivity type ions doped in the region 101 include boron ions or boron fluoride ions; the first conductivity type ions doped in the second implantation region 102 include aluminum ions.
  • the source region 103 is formed on the surface layer of the first injection region 101;
  • the gate oxide layer 301 and the gate electrode 302 are sequentially stacked on the front surface of the N-drift layer 100c, and the gate electrode 302 overlaps with the first injection region 103 and the source region 104.
  • the first injection region 103 is laterally opposite to the third injection region.
  • the second implant region 102 extends further from the bottom of the gate 302 .
  • the MOSFET device and its manufacturing method of the present invention first form a first implantation region that is easy to diffuse, and then sequentially form a second implantation region that is not easily diffused and has a deeper junction.
  • the first implantation region is activated.
  • implanted region, thereby forming the desired Well region the second implantation region is used to deepen the depth of the well region, thereby avoiding the destruction of the substrate surface at the channel caused by directly forming the P well through multiple Al ion implantations in the prior art, resulting in the device channel surface Rough problem to achieve high conduction performance of the device.
  • the same mask layer can be used for ion implantation in the first implantation region, the second implantation region and the source region, which makes the process simple and can effectively reduce the number of photolithography times.

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Abstract

本发明提供一种MOSFET器件及其制造方法，先形成易于扩散的第一注入区，后依次形成不易扩散且结更深的第二注入区，在完成源区等离子注入后，激活第一注入区，从而通过第一注入区的结扩散的方式形成所需的阱区，第二注入区用于加深阱区的深度，由此避免现有技术中直接通过多次Al离子注入来形成P阱时导致沟道处的衬底表面破环，导致器件沟道表面粗糙的问题，实现器件的高导通性能。此外，第一注入区、第二注入区以及源区的离子注入能采用同一掩膜层，工艺实现简单，且能有效减少光刻次数。

Description

MOSFET器件及其制造方法 技术领域
本发明涉及MOSFET器件制造技术领域，特别涉及一种MOSFET器件及其制造方法。
背景技术
碳化硅(SiC)MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)器件具有开关速度快、导通电阻小等优势，且在较小的漂移层厚度可以实现较高的击穿电压水平，减小功率开关模块的体积，降低能耗，在功率开关、转换器等应用领域中优势明显。
由于Al(铝)离子注入在SiC内扩散弱，因此现有平面栅SiC MOSFET工艺中，其通常是先通过多次Al离子注入的方法来获得一定深度的P阱，之后通过离子注入在P阱中形成N+源区、P+体区(又称为P+接触区)等。
但是多次Al离子注入将平面栅SiC MOSFET沟道处的SiC表面破环，导致P阱沟道表面粗糙，增加了沟道散射，限制了沟道载流子迁移率的提高。
上述问题也存在于其他使用多次Al离子注入来形成P阱的平面MOSFET工艺中。
发明内容
本发明的目的在于提供一种MOSFET器件及其制造方法，能够避免离子注入对P阱沟道表面的破坏，以实现器件的高导通性能。
为实现上述目的，本发明提供一种MOSFET器件的制造方法，其包括以下步骤：
提供衬底，在所述衬底的正面表层中注入第一导电类型的第一阱离子，以形成第一注入区；
在所述第一注入区下方的所述衬底中注入第一导电类型的第二阱离子，以形成第二注入区；
在所述第一注入区的表层中注入第二导电类型的源离子，以形成源区；
激活所述第一注入区中的第一阱离子，使得所述第一注入区的结在横向上扩散至所需宽度，且纵向上与所述第二注入区相接，以形成所需的阱区；
在所述衬底的正面上形成依次层叠的栅氧化层和栅极，所述第一注入区与所述栅氧化层接触的区域作为MOSFET器件的沟道。
可选地，在所述衬底的正面表层中注入所述第一阱离子之前，还在所述衬底的正面上形成用于定义阱区的图案化掩膜层；之后，以所述图案化掩膜层为掩摸，依次在所述衬底中注入所述第一阱离子、所述第二阱离子和所述源离子。
可选地，在形成所述源区之后且在激活所述第一注入区中的第一阱离子之前，还包括：
去除所述图案化掩膜层；
在所述源区的部分区域中注入第一导电类型的体区离子，形成体区，所述体区深入到部分所述第一注入区，以将所述源区和所述第一注入区短接。
可选地，所述第一阱离子包括硼离子或氟化硼离子；所述第二阱离子包括铝离子。
可选地，所述第一阱离子的注入工艺参数包括：注入能量为50keV～300keV，注入剂量为1E11/cm2～6E14/cm2。
可选地，通过退火工艺激活所述第一注入区中的第一阱离子，退火温度为1500℃～1900℃，退火时间为2min～200min。
可选地，所述衬底包括第二导电类型的碳化硅层，所述第一注入区和所述第二注入区均形成在所述碳化硅层中。
可选地，所述的制造方法还包括：
在所述衬底的正面上形成层间介质层，所述层间介质层将所述栅极掩埋在内并暴露出所述源区的部分区域；
在所述层间介质层上形成源极金属层，所述源极金属层与所述源区电性连接；以及
在所述衬底的背面上形成漏极金属层。
基于同一发明构思，本发明还提供一种MOSFET器件，其包括：
衬底；
第一导电类型的阱区，所述阱区包括自上而下形成的第一注入区和第二注入区，所述第一注入区形成在所述衬底的正面的部分区域的表层中，所述第二注入区形成在所述第一注入区底部下方的所述衬底中，且所述第一注入区在纵向上扩散至与所述第二注入区相接；
源区，形成在所述第一注入区的表层；以及
栅氧化层和栅极，依次层叠在所述衬底的正面上，且所述栅极与所述第一注入区和所述源区均有接触，所述第一注入区在横向上相对所述第二注入区在所述栅极底部延伸更远。
可选地，所述衬底包括第二导电类型的碳化硅层，所述第一注入区和所述第二注入区均形成在所述碳化硅层中；所述第一注入区中掺杂的第一导电类型离子包括硼离子或氟化硼离子；所述第二注入区中掺杂的第一导电类型离子包括铝离子
与现有技术相比，本发明的技术方案至少具有以下有益效果之一：
1、先形成易于扩散的第一注入区，后依次形成不易扩散且结更深的第二注入区，在完成源区等离子注入后，激活第一注入区，从而通过第一注入区的结扩散的方式形成所需的阱区，第二注入区用于加深阱区的深度，由此避免现有技术中直接通过多次Al离子注入来形成P阱时导致沟道处的衬底表面破环，导致器件沟道表面粗糙的问题，实现器件的高导通性能。
2、第一注入区、第二注入区以及源区的离子注入能采用同一掩膜层，工艺实现简单，且能有效减少光刻次数。
附图说明
本领域的普通技术人员将会理解，提供的附图用于更好地理解本发明，而不对本发明的范围构成任何限定。其中：
图1是本发明一实施例的MOSFET器件的制造方法流程示意图。
图2是图1所示的MOSFET器件的制造方法中的器件结构剖面示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的 理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。应当明白，当元件或层被称为"在…上"、"连接到"其它元件或层时，其可以直接地在其它元件或层上、连接其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为"直接在…上"、"直接连接到"其它元件或层时，则不存在居间的元件或层。尽管可使用术语第一、第二等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。空间关系术语例如“在……之下”、“在下面”、“下面的”、“在……之上”、“在上面”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在……之下”、“在下面”、“下面的”元件或特征将取向为在其它元件或特征“上”。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的"一"、"一个"和"所述/该"也意图包括复数形式，除非上下文清楚的指出另外的方式。还应明白术语“包括”用于确定可以特征、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语"和/或"包括相关所列项目的任何及所有组合。
以下结合附图和具体实施例对本发明提出的技术方案作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采 用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图1，本发明一实施例提供一种MOSFET器件的制造方法，其包括以下步骤：
S1，提供衬底，在所述衬底的正面表层中注入第一导电类型(例如为P型)的第一阱离子，以形成第一注入区；
S2，在所述第一注入区下方的所述衬底中注入第一导电类型的第二阱离子，以形成第二注入区；
S3，在所述第一注入区的表层中注入第二导电类型(例如为N型)的源离子，以形成源区；
S4，激活所述第一注入区中的第一阱离子，使得所述第一注入区的结在横向上扩散至所需宽度，且纵向上与所述第二注入区相接，以形成所需的阱区；
S5，在所述衬底的正面上形成依次层叠的栅氧化层和栅极，所述第一注入区与所述栅氧化层接触的区域作为MOSFET器件的沟道。
请参考图2中的(A)，在步骤S1中，可以提供碳化硅、硅等任意合适的半导体材料来形成衬底100。例如，提供的衬底100为N型的碳化硅衬底，且从下到上有三层，依次为N+基底100a、缓冲层100b和N-漂移层100c，N-漂移层100c的N型离子的掺杂浓度低于N+基底100a中的N型离子的掺杂浓度。
具体地，请参考图2中的(A)，在S1步骤中，首先，可以先对衬底100进行表面清洗和烘干；然后，在N-漂移层100c上沉积掩膜层材料，可以选自例如多晶硅(poly Si)、单晶硅(Si)、二氧化硅(SiO2)、氮化硅(SiN)等中的一种或多种，可以是单层膜，也可以是多种不同材料的膜的叠加，对该掩膜层材料进行光刻和刻蚀，以形成用于定义待形成的P阱的图案化掩膜层200。本示例中，在图案化掩膜层200的两侧均定义出了待形成P阱注入窗口(未图示)；接着，以图案化掩膜层200为掩膜，对N-漂移层100c的表层注入P型的第一阱离子，以在图案化掩膜层200两侧的N-漂移层100c的表层中形成第一注入区101。该步骤中选用的第一阱离子是能够在N-漂移层100c中 形成空穴，且能在高温下相对于后续的第二阱离子和源离子更容易发生扩散的离子。作为一种示例，第一阱离子为硼离子或氟化硼离子，注入方向可以是垂直于N-漂移层100c表面，注入能量为50keV～300keV(例如100keV、200keV等等)，注入剂量为1E11/cm2～6E14/cm2(例如5E12/cm2、1E13/cm2等等)。
请参考图2中的(B)，在步骤S2中，以图案化掩膜层200为掩膜，对第一注入区101下方的N-漂移层100c中注入P型的第二阱离子，以在图案化掩膜层200两侧的第一注入区101下方的N-漂移层100c中形成第二注入区102，由此第二注入区102可以形成比第一注入区101更深的结。作为一种示例，可以根据P阱设计的深度要求和宽度要求，通过多次铝(Al)离子注入，对第一注入区101下方的N-漂移层100c进行垂直地或倾斜地离子注入，注入温度为400℃～1000℃(例如500℃、800℃等等)，注入能量为200keV～500keV(例如300keV、400keV等等)，注入剂量为1E11/cm2～6E14/cm2(例如5E12/cm2、1E13/cm2、1E14/cm2等等)。
请参考图2中的(C)，在步骤S3中，以图案化掩膜层200为掩膜，根据源区设计的深度要求和宽度要求，对第一注入区101的表层垂直地或者倾斜地注入N型的源离子，以在图案化掩膜层200两侧的第一注入区101的表层中形成源区103。作为一种示例，N型的源离子包括磷(P)离子、砷(As)离子、氮(N)离子等中的至少一种，注入能量为50keV～300keV(例如100keV、200keV等等)，注入剂量为1E14/cm2～1E16/cm2(例如5E14/cm2、1E15/cm2、5E15/cm2等等)。
请参考图2中的(D)，在步骤S3中，可选地，在形成源区103之后,去除图案化掩膜层200，在源区103的部分区域中注入P型的体区离子，形成体区104(又称为接触区)，体区104的底部深入到部分第一注入区101，以将源区103和第一注入区101短接，且其P型离子的掺杂浓度高于第一注入区101。作为一种示例，体区离子可以包括硼离子、氟化硼离子和铝离子中的至少一种，注入能量为50keV～300keV(例如100keV、200keV等等)，注入剂量为1E14/cm2～1E16/cm2(例如5E14/cm2、1E15/cm2、5E15/cm2等等)。
请参考图2中的(E)，在步骤S4中，通过高温退火工艺对衬底100进行 退火，以激活第一注入区101中的第一阱离子，同时也激活第二注入区102中的第二阱离子和源区103中的N型离子体区104中的P型离子；退火温度为1500℃～1900℃(例如1650℃、1700℃、1800℃等等)，退火时间为2min～200min(例如10min、20min、50min、100min等等)。该高温退火过程使得第一注入区101中的硼离子等第一阱离子发生扩散，扩散后的第一注入区101’在纵向上底部与第二注入区102的顶部相接，横向上扩展至P阱所需的宽度，以在后续提供所需的沟道宽度。而且，第二注入区102中的第二阱离子和源区103中的N型离子体区104中的P型离子均相对第一注入区101中的第一阱离子的扩散较弱，两个扩散后的第一注入区101’之间的N-漂移层101c作为耗尽区。
该步骤中，所需的阱区由上部的扩散后的第一注入区101’和下部的第二注入区102组成，且由于所需的沟道是通过第一注入区101扩散形成的，因此沟道表面能大大减少粗糙，进而能减少最终制得的MOSFET器件的沟道电子发生的界面散射，从而提高其沟道迁移率。
请参考图2中的(F)，在步骤S5中，首先，可以采用热氧化工艺或化学气相沉积等合适的栅氧工艺，在体区104、源区103、扩散后的第一注入区101’和N-漂移层100c的正面上形成栅氧化层301；然后可以在栅氧化层301的表面上沉积栅极材料层，并对沉积的栅极材料层和栅氧化层301进行光刻和刻蚀，形成栅极302。形成的栅极302与扩散后的第一注入区101’和源区104均有交叠，且扩散后的第一注入区101’与栅氧化层301接触的区域作为MOSFET器件的沟道。
本步骤中，由于步骤S4中通过扩散的方式形成P阱，能够有效避免沟道表面粗糙，且也能保证用作耗尽区的N-漂移层100c的SiC结晶质量完好，因此能保障所形成的栅氧化层301的质量，降低沟道缺陷密度，使得器件的温漂性能进一步改善，进一步提高器件的可靠性。
进一步可选地，在形成栅极302之后，首先，通过化学气相沉积工艺等，在衬底100的正面上覆盖层间介质层400，层间介质层400可以是单层介质膜结构，也可以是多层介质膜层叠而成的结构。接着，对该层间介质层400进行光刻和刻蚀，以图案化该层间介质层400，图案化后的层间介质层400可以 将所述栅极302掩埋在内并暴露出源区103的部分区域。然后，通过金属溅射沉积或者蒸镀等合适的工艺，在层间介质层400上形成源极金属层500(例如铜、铝、金等等一种金属材料或者合金)，该源极金属层500与源区103和体区104均电性连接。之后，在N+基底100a的背面上形成漏极金属层(未图示)。
本实施例的MOSFET器件的制造方法，通过扩散的方式形成所需的阱区，一方面，沟道表面能大大减少粗糙，减少沟道电子发生的界面散射，从而提高沟道迁移率，另一方面能改善沟道缺陷能级和栅氧质量，使得器件的温漂性能进一步改善，进一步提高器件的可靠性。
此外，第一注入区、第二注入区以及源区的离子注入能采用同一图案化掩膜层200来实施，工艺实现简单，且能有效减少光刻次数。
请参考图2中的(F)，本发明一实施例还提供一种MOSFET器件，其优选地采用本发明的MOSFET器件的制造方法来制造，该MOSFET器件包括：
衬底100，该衬底100可以是任意合适的半导体材料。例如衬底100为N型的碳化硅衬底，且从下到上有三层，依次为N+基底100a、缓冲层100b和N-漂移层100c；
第一导电类型(例如P型)的阱区，该阱区包括自上而下形成的第一注入区101和第二注入区102，第一注入区101形成在N-漂移层100c正面的部分区域的表层中，第二注入区102形成在第一注入区101底部下方的N-漂移层100c中，且第一注入区101在纵向上扩散至与第二注入区102相接；第一注入区101中掺杂的第一导电类型离子包括硼离子或氟化硼离子；第二注入区102中掺杂的第一导电类型离子包括铝离子。
源区103形成在第一注入区101的表层；
栅氧化层301和栅极302，依次层叠在N-漂移层100c的正面上，且栅极302与第一注入区103和源区104均有交叠，第一注入区103在横向上相对第二注入区102在栅极302底部延伸更远。
综上所述，本发明的MOSFET器件及其制造方法，先形成易于扩散的第一注入区，后依次形成不易扩散且结更深的第二注入区，在完成源区等离子注入后，激活第一注入区，从而通过第一注入区的结扩散的方式形成所需的 阱区，第二注入区用于加深阱区的深度，由此避免现有技术中直接通过多次Al离子注入来形成P阱时导致沟道处的衬底表面破环，导致器件沟道表面粗糙的问题，实现器件的高导通性能。此外，第一注入区、第二注入区以及源区的离子注入能采用同一掩膜层，工艺实现简单，且能有效减少光刻次数。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于本发明技术方案的保护范围。

Claims (10)

  1. 一种MOSFET器件的制造方法，其特征在于，包括：
    提供衬底，在所述衬底的正面表层中注入第一导电类型的第一阱离子，以形成第一注入区；
    在所述第一注入区下方的所述衬底中注入第一导电类型的第二阱离子，以形成第二注入区；
    在所述第一注入区的表层中注入第二导电类型的源离子，以形成源区；
    激活所述第一注入区中的第一阱离子，使得所述第一注入区的结在横向上扩散至所需宽度，且纵向上与所述第二注入区相接，以形成所需的阱区；以及
    在所述衬底的正面上形成依次层叠的栅氧化层和栅极，所述第一注入区与所述栅氧化层接触的区域作为MOSFET器件的沟道。
  2. 如权利要求1所述的制造方法，其特征在于，在所述衬底的正面表层中注入所述第一阱离子之前，所述制造方法还包括：
    在所述衬底的正面上形成用于定义阱区的图案化掩膜层；
    以所述图案化掩膜层为掩摸，依次在所述衬底中注入所述第一阱离子、所述第二阱离子和所述源离子。
  3. 如权利要求2所述的制造方法，其特征在于，在形成所述源区之后且在激活所述第一注入区中的第一阱离子之前，所述制造方法还包括：
    去除所述图案化掩膜层；
    在所述源区的部分区域中注入第一导电类型的体区离子，形成体区，所述体区深入到部分所述第一注入区，以将所述源区和所述第一注入区短接。
  4. 如权利要求1所述的制造方法，其特征在于，所述第一阱离子包括硼离子或氟化硼离子；所述第二阱离子包括铝离子。
  5. 如权利要求4所述的制造方法，其特征在于，所述第一阱离子的注入工艺参数包括：注入能量为50keV～300keV，注入剂量为1E11/cm2～6E14/cm2。
  6. 如权利要求4所述的制造方法，其特征在于，通过退火工艺激活所述第一注入区中的第一阱离子，退火温度为1500℃～1900℃，退火时间为2min～ 200min。
  7. 如权利要求4所述的制造方法，其特征在于，所述衬底包括第二导电类型的碳化硅层，所述第一注入区和所述第二注入区均形成在所述碳化硅层中。
  8. 如权利要求1-7中任一项所述的制造方法，其特征在于，还包括：
    在所述衬底的正面上形成层间介质层，所述层间介质层将所述栅极掩埋在内并暴露出所述源区的部分区域；
    在所述层间介质层上形成源极金属层，所述源极金属层与所述源区电性连接；以及
    在所述衬底的背面上形成漏极金属层。
  9. 一种MOSFET器件，其特征在于，包括：
    衬底；
    第一导电类型的阱区，所述阱区包括自上而下形成的第一注入区和第二注入区，所述第一注入区形成在所述衬底的正面的部分区域的表层中，所述第二注入区形成在所述第一注入区底部下方的所述衬底中，且所述第一注入区在纵向上与所述第二注入区相接；
    源区，形成在所述第一注入区的表层；以及
    栅氧化层和栅极，依次层叠在所述衬底的正面上，且所述栅极与所述第一注入区和所述源区均有接触，所述第一注入区在横向上相对所述第二注入区在所述栅极底部延伸更远。
  10. 如权利要求9所述的MOSFET器件，其特征在于，所述衬底包括第二导电类型的碳化硅层，所述第一注入区和所述第二注入区均形成在所述碳化硅层中；所述第一注入区中掺杂的第一导电类型的第一阱离子包括硼离子或氟化硼离子；所述第二注入区中掺杂的第一导电类型的第二阱离子包括铝离子。
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