SE504041C2 - Integrerat kretsarrangemang för provning - Google Patents

Integrerat kretsarrangemang för provning

Info

Publication number
SE504041C2
SE504041C2 SE9500934A SE9500934A SE504041C2 SE 504041 C2 SE504041 C2 SE 504041C2 SE 9500934 A SE9500934 A SE 9500934A SE 9500934 A SE9500934 A SE 9500934A SE 504041 C2 SE504041 C2 SE 504041C2
Authority
SE
Sweden
Prior art keywords
multiplexer
signal
test
input
output
Prior art date
Application number
SE9500934A
Other languages
English (en)
Swedish (sv)
Other versions
SE9500934D0 (sv
SE9500934L (sv
Inventor
Krzysztof Kaminski
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9500934A priority Critical patent/SE504041C2/sv
Publication of SE9500934D0 publication Critical patent/SE9500934D0/xx
Priority to AU51293/96A priority patent/AU5129396A/en
Priority to EP96907827A priority patent/EP0826176B1/de
Priority to US08/894,463 priority patent/US5894483A/en
Priority to JP8527509A priority patent/JPH11502019A/ja
Priority to PCT/SE1996/000286 priority patent/WO1996028781A1/en
Priority to DE69622172T priority patent/DE69622172T2/de
Publication of SE9500934L publication Critical patent/SE9500934L/
Publication of SE504041C2 publication Critical patent/SE504041C2/sv

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
SE9500934A 1995-03-16 1995-03-16 Integrerat kretsarrangemang för provning SE504041C2 (sv)

Priority Applications (7)

Application Number Priority Date Filing Date Title
SE9500934A SE504041C2 (sv) 1995-03-16 1995-03-16 Integrerat kretsarrangemang för provning
AU51293/96A AU5129396A (en) 1995-03-16 1996-03-04 Integrated circuit arrangement
EP96907827A EP0826176B1 (de) 1995-03-16 1996-03-04 Integrierte schaltungsanordnung
US08/894,463 US5894483A (en) 1995-03-16 1996-03-04 Integrated circuit arrangement
JP8527509A JPH11502019A (ja) 1995-03-16 1996-03-04 集積回路構造
PCT/SE1996/000286 WO1996028781A1 (en) 1995-03-16 1996-03-04 Integrated circuit arrangement
DE69622172T DE69622172T2 (de) 1995-03-16 1996-03-04 Integrierte schaltungsanordnung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9500934A SE504041C2 (sv) 1995-03-16 1995-03-16 Integrerat kretsarrangemang för provning

Publications (3)

Publication Number Publication Date
SE9500934D0 SE9500934D0 (sv) 1995-03-16
SE9500934L SE9500934L (sv) 1996-09-17
SE504041C2 true SE504041C2 (sv) 1996-10-21

Family

ID=20397567

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9500934A SE504041C2 (sv) 1995-03-16 1995-03-16 Integrerat kretsarrangemang för provning

Country Status (7)

Country Link
US (1) US5894483A (de)
EP (1) EP0826176B1 (de)
JP (1) JPH11502019A (de)
AU (1) AU5129396A (de)
DE (1) DE69622172T2 (de)
SE (1) SE504041C2 (de)
WO (1) WO1996028781A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6266801B1 (en) * 1998-09-15 2001-07-24 Adaptec, Inc. Boundary-scan cells with improved timing characteristics
JP4748337B2 (ja) * 2000-09-26 2011-08-17 大日本印刷株式会社 半導体回路のテスト用設計回路パタン
US7246282B2 (en) * 2003-06-25 2007-07-17 Hewlett-Packard Development Company, L.P. Bypassing a device in a scan chain

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0358371B1 (de) * 1988-09-07 1998-03-11 Texas Instruments Incorporated Erweiterte Prüfschaltung
EP0358365B1 (de) * 1988-09-07 1998-10-21 Texas Instruments Incorporated Prüf-Puffer/Register
EP0628831B1 (de) * 1988-09-07 1998-03-18 Texas Instruments Incorporated Bidirektionale-Boundary-Scan-Testzelle
JP2676169B2 (ja) * 1989-12-27 1997-11-12 三菱電機株式会社 スキャンパス回路
US5355369A (en) * 1991-04-26 1994-10-11 At&T Bell Laboratories High-speed integrated circuit testing with JTAG
DE69226401T2 (de) * 1991-05-23 1999-03-04 Motorola Gmbh Ausführung der IEEE 1149.1-Schnittstellenarchitektur
GB9111179D0 (en) * 1991-05-23 1991-07-17 Motorola Gmbh An implementation of the ieee 1149.1 boundary-scan architecture
DE4232271C1 (de) * 1992-09-25 1994-02-17 Siemens Ag Elektronischer Baustein mit einer Schieberegisterprüfarchitektur (Boundary-Scan)

Also Published As

Publication number Publication date
DE69622172D1 (de) 2002-08-08
AU5129396A (en) 1996-10-02
US5894483A (en) 1999-04-13
WO1996028781A1 (en) 1996-09-19
SE9500934D0 (sv) 1995-03-16
EP0826176A1 (de) 1998-03-04
DE69622172T2 (de) 2003-02-13
EP0826176B1 (de) 2002-07-03
JPH11502019A (ja) 1999-02-16
SE9500934L (sv) 1996-09-17

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