DE69226401T2 - Ausführung der IEEE 1149.1-Schnittstellenarchitektur - Google Patents

Ausführung der IEEE 1149.1-Schnittstellenarchitektur

Info

Publication number
DE69226401T2
DE69226401T2 DE1992626401 DE69226401T DE69226401T2 DE 69226401 T2 DE69226401 T2 DE 69226401T2 DE 1992626401 DE1992626401 DE 1992626401 DE 69226401 T DE69226401 T DE 69226401T DE 69226401 T2 DE69226401 T2 DE 69226401T2
Authority
DE
Germany
Prior art keywords
input
flip
flop
receiving
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE1992626401
Other languages
English (en)
Other versions
DE69226401D1 (de
Inventor
Reinhard Hahn
Norbert Hummer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB919111179A external-priority patent/GB9111179D0/en
Application filed by Motorola GmbH filed Critical Motorola GmbH
Publication of DE69226401D1 publication Critical patent/DE69226401D1/de
Application granted granted Critical
Publication of DE69226401T2 publication Critical patent/DE69226401T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
DE1992626401 1991-05-23 1992-04-30 Ausführung der IEEE 1149.1-Schnittstellenarchitektur Expired - Lifetime DE69226401T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB919111179A GB9111179D0 (en) 1991-05-23 1991-05-23 An implementation of the ieee 1149.1 boundary-scan architecture
GB9127379A GB2256058A (en) 1991-05-23 1991-12-24 Ieee 1149.1 boundary- scan architecture

Publications (2)

Publication Number Publication Date
DE69226401D1 DE69226401D1 (de) 1998-09-03
DE69226401T2 true DE69226401T2 (de) 1999-03-04

Family

ID=26298940

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1992626401 Expired - Lifetime DE69226401T2 (de) 1991-05-23 1992-04-30 Ausführung der IEEE 1149.1-Schnittstellenarchitektur

Country Status (3)

Country Link
EP (1) EP0514700B1 (de)
JP (1) JP3207245B2 (de)
DE (1) DE69226401T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI100136B (fi) * 1993-10-01 1997-09-30 Nokia Telecommunications Oy Menetelmä integroidun piirin testaamiseksi sekä integroitu piiri
US6173428B1 (en) * 1994-11-16 2001-01-09 Cray Research, Inc. Apparatus and method for testing using clocked test access port controller for level sensitive scan designs
SE504041C2 (sv) * 1995-03-16 1996-10-21 Ericsson Telefon Ab L M Integrerat kretsarrangemang för provning
US6594789B2 (en) * 1997-09-16 2003-07-15 Texas Instruments Incorporated Input data capture boundary cell connected to target circuit output
JP2002259207A (ja) * 2001-03-02 2002-09-13 Fujitsu Ltd 情報処理装置及び信号処理装置並びにインタフェース装置
US7506228B2 (en) 2006-02-14 2009-03-17 Atmel Corporation Measuring the internal clock speed of an integrated circuit
FR2972087B1 (fr) * 2011-02-24 2014-05-30 Dolphin Integration Sa Circuit de bascule commandee par impulsions
US11547192B2 (en) 2019-05-09 2023-01-10 Renee Boncore Scalzini Bag organizer systems and methods of assembly

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4504784A (en) * 1981-07-02 1985-03-12 International Business Machines Corporation Method of electrically testing a packaging structure having N interconnected integrated circuit chips
US5042034A (en) * 1989-10-27 1991-08-20 International Business Machines Corporation By-pass boundary scan design

Also Published As

Publication number Publication date
DE69226401D1 (de) 1998-09-03
JP3207245B2 (ja) 2001-09-10
EP0514700A2 (de) 1992-11-25
EP0514700A3 (de) 1995-01-11
JPH05180911A (ja) 1993-07-23
EP0514700B1 (de) 1998-07-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US

8328 Change in the person/name/address of the agent

Representative=s name: SCHUMACHER & WILLSAU, PATENTANWALTSSOZIETAET, 80335

R071 Expiry of right

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