DE69622172D1 - Integrierte schaltungsanordnung - Google Patents

Integrierte schaltungsanordnung

Info

Publication number
DE69622172D1
DE69622172D1 DE69622172T DE69622172T DE69622172D1 DE 69622172 D1 DE69622172 D1 DE 69622172D1 DE 69622172 T DE69622172 T DE 69622172T DE 69622172 T DE69622172 T DE 69622172T DE 69622172 D1 DE69622172 D1 DE 69622172D1
Authority
DE
Germany
Prior art keywords
integrated circuit
circuit arrangement
arrangement
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69622172T
Other languages
English (en)
Other versions
DE69622172T2 (de
Inventor
Krzysztof Kaminski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of DE69622172D1 publication Critical patent/DE69622172D1/de
Application granted granted Critical
Publication of DE69622172T2 publication Critical patent/DE69622172T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541Scan latches or cell details
DE69622172T 1995-03-16 1996-03-04 Integrierte schaltungsanordnung Expired - Lifetime DE69622172T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9500934A SE504041C2 (sv) 1995-03-16 1995-03-16 Integrerat kretsarrangemang för provning
PCT/SE1996/000286 WO1996028781A1 (en) 1995-03-16 1996-03-04 Integrated circuit arrangement

Publications (2)

Publication Number Publication Date
DE69622172D1 true DE69622172D1 (de) 2002-08-08
DE69622172T2 DE69622172T2 (de) 2003-02-13

Family

ID=20397567

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69622172T Expired - Lifetime DE69622172T2 (de) 1995-03-16 1996-03-04 Integrierte schaltungsanordnung

Country Status (7)

Country Link
US (1) US5894483A (de)
EP (1) EP0826176B1 (de)
JP (1) JPH11502019A (de)
AU (1) AU5129396A (de)
DE (1) DE69622172T2 (de)
SE (1) SE504041C2 (de)
WO (1) WO1996028781A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6266801B1 (en) * 1998-09-15 2001-07-24 Adaptec, Inc. Boundary-scan cells with improved timing characteristics
JP4748337B2 (ja) * 2000-09-26 2011-08-17 大日本印刷株式会社 半導体回路のテスト用設計回路パタン
US7246282B2 (en) * 2003-06-25 2007-07-17 Hewlett-Packard Development Company, L.P. Bypassing a device in a scan chain

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0358365B1 (de) * 1988-09-07 1998-10-21 Texas Instruments Incorporated Prüf-Puffer/Register
EP0358371B1 (de) * 1988-09-07 1998-03-11 Texas Instruments Incorporated Erweiterte Prüfschaltung
DE68928613T2 (de) * 1988-09-07 1998-09-24 Texas Instruments Inc Bidirektionale-Boundary-Scan-Testzelle
JP2676169B2 (ja) * 1989-12-27 1997-11-12 三菱電機株式会社 スキャンパス回路
US5355369A (en) * 1991-04-26 1994-10-11 At&T Bell Laboratories High-speed integrated circuit testing with JTAG
GB9111179D0 (en) * 1991-05-23 1991-07-17 Motorola Gmbh An implementation of the ieee 1149.1 boundary-scan architecture
DE69226401T2 (de) * 1991-05-23 1999-03-04 Motorola Gmbh Ausführung der IEEE 1149.1-Schnittstellenarchitektur
DE4232271C1 (de) * 1992-09-25 1994-02-17 Siemens Ag Elektronischer Baustein mit einer Schieberegisterprüfarchitektur (Boundary-Scan)

Also Published As

Publication number Publication date
WO1996028781A1 (en) 1996-09-19
US5894483A (en) 1999-04-13
SE9500934L (sv) 1996-09-17
SE9500934D0 (sv) 1995-03-16
JPH11502019A (ja) 1999-02-16
DE69622172T2 (de) 2003-02-13
EP0826176B1 (de) 2002-07-03
SE504041C2 (sv) 1996-10-21
EP0826176A1 (de) 1998-03-04
AU5129396A (en) 1996-10-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition