SE457179B - Foerfarande foer framstaellning av en avsmalnande oeppning i en passiverande glasbelaeggning anordnad oever ytan paa en halvledarstomme - Google Patents

Foerfarande foer framstaellning av en avsmalnande oeppning i en passiverande glasbelaeggning anordnad oever ytan paa en halvledarstomme

Info

Publication number
SE457179B
SE457179B SE8202597A SE8202597A SE457179B SE 457179 B SE457179 B SE 457179B SE 8202597 A SE8202597 A SE 8202597A SE 8202597 A SE8202597 A SE 8202597A SE 457179 B SE457179 B SE 457179B
Authority
SE
Sweden
Prior art keywords
layer
temperature
doped
semiconductor body
oxide layers
Prior art date
Application number
SE8202597A
Other languages
English (en)
Swedish (sv)
Other versions
SE8202597L (sv
Inventor
D W Flatley
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22980524&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=SE457179(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Rca Corp filed Critical Rca Corp
Publication of SE8202597L publication Critical patent/SE8202597L/xx
Publication of SE457179B publication Critical patent/SE457179B/sv

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)
SE8202597A 1981-04-28 1982-04-26 Foerfarande foer framstaellning av en avsmalnande oeppning i en passiverande glasbelaeggning anordnad oever ytan paa en halvledarstomme SE457179B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/258,431 US4349584A (en) 1981-04-28 1981-04-28 Process for tapering openings in ternary glass coatings

Publications (2)

Publication Number Publication Date
SE8202597L SE8202597L (sv) 1982-10-29
SE457179B true SE457179B (sv) 1988-12-05

Family

ID=22980524

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8202597A SE457179B (sv) 1981-04-28 1982-04-26 Foerfarande foer framstaellning av en avsmalnande oeppning i en passiverande glasbelaeggning anordnad oever ytan paa en halvledarstomme

Country Status (9)

Country Link
US (1) US4349584A (enExample)
JP (1) JPS57186343A (enExample)
CA (1) CA1189426A (enExample)
DE (1) DE3215101C2 (enExample)
GB (1) GB2097582B (enExample)
IN (1) IN155987B (enExample)
IT (1) IT1218317B (enExample)
SE (1) SE457179B (enExample)
YU (1) YU44340B (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4455325A (en) * 1981-03-16 1984-06-19 Fairchild Camera And Instrument Corporation Method of inducing flow or densification of phosphosilicate glass for integrated circuits
US4433008A (en) * 1982-05-11 1984-02-21 Rca Corporation Doped-oxide diffusion of phosphorus using borophosphosilicate glass
US4420503A (en) * 1982-05-17 1983-12-13 Rca Corporation Low temperature elevated pressure glass flow/re-flow process
US4476621A (en) * 1983-02-01 1984-10-16 Gte Communications Products Corporation Process for making transistors with doped oxide densification
US4575921A (en) * 1983-11-04 1986-03-18 General Motors Corporation Silicon nitride formation and use in self-aligned semiconductor device manufacturing method
US4528211A (en) * 1983-11-04 1985-07-09 General Motors Corporation Silicon nitride formation and use in self-aligned semiconductor device manufacturing method
US4582745A (en) * 1984-01-17 1986-04-15 Rca Corporation Dielectric layers in multilayer refractory metallization structure
DE3425531A1 (de) * 1984-07-11 1986-01-16 Siemens AG, 1000 Berlin und 8000 München Verfahren zum verfliessenlassen von dotierten sio(pfeil abwaerts)2(pfeil abwaerts)-schichten bei der herstellung von integrierten mos-halbleiterschaltungen
US4546016A (en) * 1984-08-06 1985-10-08 Rca Corporation Deposition of borophosphosilicate glass
GB2168340B (en) * 1984-12-13 1988-11-02 Stc Plc Contacting an integrated circuit with a metallisation pattern
US4743564A (en) * 1984-12-28 1988-05-10 Kabushiki Kaisha Toshiba Method for manufacturing a complementary MOS type semiconductor device
EP0204182B1 (de) * 1985-05-22 1991-06-05 Siemens Aktiengesellschaft Verfahren zum Herstellen von mit Bor und Phosphor dotierten Siliziumoxid-Schichten für integrierte Halbleiterschaltungen
GB8523373D0 (en) * 1985-09-21 1985-10-23 Stc Plc Via profiling in integrated circuits
US4755479A (en) * 1986-02-17 1988-07-05 Fujitsu Limited Manufacturing method of insulated gate field effect transistor using reflowable sidewall spacers
JPS6381948A (ja) * 1986-09-26 1988-04-12 Toshiba Corp 多層配線半導体装置
EP0369336A3 (en) * 1988-11-14 1990-08-22 National Semiconductor Corporation Process for fabricating bipolar and cmos transistors on a common substrate
JPH0793354B2 (ja) * 1988-11-28 1995-10-09 株式会社東芝 半導体装置の製造方法
US5747389A (en) * 1991-04-30 1998-05-05 Intel Corporation Crack resistant passivation layer
US5424570A (en) * 1992-01-31 1995-06-13 Sgs-Thomson Microelectronics, Inc. Contact structure for improving photoresist adhesion on a dielectric layer
EP0562625B1 (en) * 1992-03-27 1997-06-04 Matsushita Electric Industrial Co., Ltd. A semiconductor device and process
US6239017B1 (en) 1998-09-18 2001-05-29 Industrial Technology Research Institute Dual damascene CMP process with BPSG reflowed contact hole

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3481781A (en) * 1967-03-17 1969-12-02 Rca Corp Silicate glass coating of semiconductor devices
US3833919A (en) * 1972-10-12 1974-09-03 Ncr Multilevel conductor structure and method
US3925572A (en) * 1972-10-12 1975-12-09 Ncr Co Multilevel conductor structure and method
JPS5922378B2 (ja) * 1975-08-13 1984-05-26 株式会社東芝 半導体装置の製造方法
US4091407A (en) * 1976-11-01 1978-05-23 Rca Corporation Combination glass/low temperature deposited Siw Nx Hy O.sub.z
US4097889A (en) * 1976-11-01 1978-06-27 Rca Corporation Combination glass/low temperature deposited Siw Nx Hy O.sub.z
US4273805A (en) * 1978-06-19 1981-06-16 Rca Corporation Passivating composite for a semiconductor device comprising a silicon nitride (Si1 3N4) layer and phosphosilicate glass (PSG) layer
GB2031225B (en) * 1978-09-15 1983-07-20 Westinghouse Electric Corp Glass-sealed thyristor junctions
CA1174285A (en) * 1980-04-28 1984-09-11 Michelangelo Delfino Laser induced flow of integrated circuit structure materials

Also Published As

Publication number Publication date
IT8220463A0 (it) 1982-03-29
SE8202597L (sv) 1982-10-29
DE3215101C2 (de) 1995-06-22
JPS57186343A (en) 1982-11-16
GB2097582B (en) 1985-10-30
DE3215101A1 (de) 1982-11-11
CA1189426A (en) 1985-06-25
US4349584A (en) 1982-09-14
YU44340B (en) 1990-06-30
YU91382A (en) 1985-04-30
IN155987B (enExample) 1985-04-20
IT1218317B (it) 1990-04-12
GB2097582A (en) 1982-11-03

Similar Documents

Publication Publication Date Title
SE457179B (sv) Foerfarande foer framstaellning av en avsmalnande oeppning i en passiverande glasbelaeggning anordnad oever ytan paa en halvledarstomme
EP0274801B1 (en) Method of manufacturing a semiconductor device of the "semiconductor on insulator" type
US5976947A (en) Method for forming dielectric within a recess
US8221642B2 (en) Methods for removing dielectric materials
EP0098687B1 (en) Method of manufacturing a semiconductor device including burying an insulating film
JP2002083797A (ja) 改善された酸化物エッチング
EP0134232A1 (en) METHOD FOR MANUFACTURING SOLAR CELLS.
US3969168A (en) Method for filling grooves and moats used on semiconductor devices
US3760242A (en) Coated semiconductor structures and methods of forming protective coverings on such structures
KR20000011599A (ko) 수소실세스퀴옥산수지로부터저유전성코팅을제조하기위한방법
US3537921A (en) Selective hydrofluoric acid etching and subsequent processing
US4420503A (en) Low temperature elevated pressure glass flow/re-flow process
US3698947A (en) Process for forming monocrystalline and poly
US3434896A (en) Process for etching silicon monoxide and etchant solutions therefor
US3432405A (en) Selective masking method of silicon during anodization
US5413678A (en) Heated SC1 solution for selective etching
JPS59182537A (ja) 半導体装置の製造方法
JPS59182538A (ja) 半導体装置およびその製造方法
JPH07507903A (ja) 集積回路および自立マイクロ構造を含むモノリシック・チップの製造方法
JPS58164238A (ja) 半導体装置の製造方法
JPH079930B2 (ja) 半導体装置の製造方法
KR950002175B1 (ko) 박막 센서용 Si 박막 형성방법
JPH01302823A (ja) 半導体基板の平坦化方法
JPS5478668A (en) Manufacture of semiconductor device
KR100335802B1 (ko) 반도체소자의소자분리막형성방법

Legal Events

Date Code Title Description
NAL Patent in force

Ref document number: 8202597-4

Format of ref document f/p: F

NUG Patent has lapsed

Ref document number: 8202597-4

Format of ref document f/p: F