IT8220463A0 - Processo per formare aperture rastremate in rivestimenti di vetro di corpi semiconduttori - Google Patents

Processo per formare aperture rastremate in rivestimenti di vetro di corpi semiconduttori

Info

Publication number
IT8220463A0
IT8220463A0 IT8220463A IT2046382A IT8220463A0 IT 8220463 A0 IT8220463 A0 IT 8220463A0 IT 8220463 A IT8220463 A IT 8220463A IT 2046382 A IT2046382 A IT 2046382A IT 8220463 A0 IT8220463 A0 IT 8220463A0
Authority
IT
Italy
Prior art keywords
semiconductor bodies
tapered openings
glass coatings
forming tapered
forming
Prior art date
Application number
IT8220463A
Other languages
English (en)
Other versions
IT1218317B (it
Inventor
Doris Winifred Flatley
Sheng Teng Hsu
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22980524&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=IT8220463(A0) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Rca Corp filed Critical Rca Corp
Publication of IT8220463A0 publication Critical patent/IT8220463A0/it
Application granted granted Critical
Publication of IT1218317B publication Critical patent/IT1218317B/it

Links

Classifications

    • H10P95/00—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
IT20463/82A 1981-04-28 1982-03-29 Processo per formare aperture rastremate in rivestimenti di vetro di corpi semiconduttori IT1218317B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/258,431 US4349584A (en) 1981-04-28 1981-04-28 Process for tapering openings in ternary glass coatings

Publications (2)

Publication Number Publication Date
IT8220463A0 true IT8220463A0 (it) 1982-03-29
IT1218317B IT1218317B (it) 1990-04-12

Family

ID=22980524

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20463/82A IT1218317B (it) 1981-04-28 1982-03-29 Processo per formare aperture rastremate in rivestimenti di vetro di corpi semiconduttori

Country Status (9)

Country Link
US (1) US4349584A (it)
JP (1) JPS57186343A (it)
CA (1) CA1189426A (it)
DE (1) DE3215101C2 (it)
GB (1) GB2097582B (it)
IN (1) IN155987B (it)
IT (1) IT1218317B (it)
SE (1) SE457179B (it)
YU (1) YU44340B (it)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4455325A (en) * 1981-03-16 1984-06-19 Fairchild Camera And Instrument Corporation Method of inducing flow or densification of phosphosilicate glass for integrated circuits
US4433008A (en) * 1982-05-11 1984-02-21 Rca Corporation Doped-oxide diffusion of phosphorus using borophosphosilicate glass
US4420503A (en) * 1982-05-17 1983-12-13 Rca Corporation Low temperature elevated pressure glass flow/re-flow process
US4476621A (en) * 1983-02-01 1984-10-16 Gte Communications Products Corporation Process for making transistors with doped oxide densification
US4528211A (en) * 1983-11-04 1985-07-09 General Motors Corporation Silicon nitride formation and use in self-aligned semiconductor device manufacturing method
US4575921A (en) * 1983-11-04 1986-03-18 General Motors Corporation Silicon nitride formation and use in self-aligned semiconductor device manufacturing method
US4582745A (en) * 1984-01-17 1986-04-15 Rca Corporation Dielectric layers in multilayer refractory metallization structure
DE3425531A1 (de) * 1984-07-11 1986-01-16 Siemens AG, 1000 Berlin und 8000 München Verfahren zum verfliessenlassen von dotierten sio(pfeil abwaerts)2(pfeil abwaerts)-schichten bei der herstellung von integrierten mos-halbleiterschaltungen
US4546016A (en) * 1984-08-06 1985-10-08 Rca Corporation Deposition of borophosphosilicate glass
GB2168340B (en) * 1984-12-13 1988-11-02 Stc Plc Contacting an integrated circuit with a metallisation pattern
US4743564A (en) * 1984-12-28 1988-05-10 Kabushiki Kaisha Toshiba Method for manufacturing a complementary MOS type semiconductor device
ATE64237T1 (de) * 1985-05-22 1991-06-15 Siemens Ag Verfahren zum herstellen von mit bor und phosphor dotierten siliziumoxid-schichten fuer integrierte halbleiterschaltungen.
GB8523373D0 (en) * 1985-09-21 1985-10-23 Stc Plc Via profiling in integrated circuits
US4755479A (en) * 1986-02-17 1988-07-05 Fujitsu Limited Manufacturing method of insulated gate field effect transistor using reflowable sidewall spacers
JPS6381948A (ja) * 1986-09-26 1988-04-12 Toshiba Corp 多層配線半導体装置
EP0369336A3 (en) * 1988-11-14 1990-08-22 National Semiconductor Corporation Process for fabricating bipolar and cmos transistors on a common substrate
JPH0793354B2 (ja) * 1988-11-28 1995-10-09 株式会社東芝 半導体装置の製造方法
US5747389A (en) * 1991-04-30 1998-05-05 Intel Corporation Crack resistant passivation layer
US5424570A (en) * 1992-01-31 1995-06-13 Sgs-Thomson Microelectronics, Inc. Contact structure for improving photoresist adhesion on a dielectric layer
DE69311184T2 (de) * 1992-03-27 1997-09-18 Matsushita Electric Ind Co Ltd Halbleitervorrichtung samt Herstellungsverfahren
US6239017B1 (en) 1998-09-18 2001-05-29 Industrial Technology Research Institute Dual damascene CMP process with BPSG reflowed contact hole

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3481781A (en) * 1967-03-17 1969-12-02 Rca Corp Silicate glass coating of semiconductor devices
US3925572A (en) * 1972-10-12 1975-12-09 Ncr Co Multilevel conductor structure and method
US3833919A (en) * 1972-10-12 1974-09-03 Ncr Multilevel conductor structure and method
JPS5922378B2 (ja) * 1975-08-13 1984-05-26 株式会社東芝 半導体装置の製造方法
US4097889A (en) * 1976-11-01 1978-06-27 Rca Corporation Combination glass/low temperature deposited Siw Nx Hy O.sub.z
US4091407A (en) * 1976-11-01 1978-05-23 Rca Corporation Combination glass/low temperature deposited Siw Nx Hy O.sub.z
US4273805A (en) * 1978-06-19 1981-06-16 Rca Corporation Passivating composite for a semiconductor device comprising a silicon nitride (Si1 3N4) layer and phosphosilicate glass (PSG) layer
GB2031225B (en) * 1978-09-15 1983-07-20 Westinghouse Electric Corp Glass-sealed thyristor junctions
CA1174285A (en) * 1980-04-28 1984-09-11 Michelangelo Delfino Laser induced flow of integrated circuit structure materials

Also Published As

Publication number Publication date
US4349584A (en) 1982-09-14
DE3215101C2 (de) 1995-06-22
CA1189426A (en) 1985-06-25
YU44340B (en) 1990-06-30
SE8202597L (sv) 1982-10-29
JPS57186343A (en) 1982-11-16
IT1218317B (it) 1990-04-12
SE457179B (sv) 1988-12-05
DE3215101A1 (de) 1982-11-11
GB2097582B (en) 1985-10-30
YU91382A (en) 1985-04-30
IN155987B (it) 1985-04-20
GB2097582A (en) 1982-11-03

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19980327