RU2001103636A - Полупроводниковый компонент с пассивирующим слоем - Google Patents

Полупроводниковый компонент с пассивирующим слоем

Info

Publication number
RU2001103636A
RU2001103636A RU2001103636/28A RU2001103636A RU2001103636A RU 2001103636 A RU2001103636 A RU 2001103636A RU 2001103636/28 A RU2001103636/28 A RU 2001103636/28A RU 2001103636 A RU2001103636 A RU 2001103636A RU 2001103636 A RU2001103636 A RU 2001103636A
Authority
RU
Russia
Prior art keywords
layer
passivating
double
structured
semiconductor base
Prior art date
Application number
RU2001103636/28A
Other languages
English (en)
Other versions
RU2195048C2 (ru
Inventor
Йозеф ВИЛЛЕР (DE)
Йозеф ВИЛЛЕР
БАССЕ Пауль-Вернер ФОН (DE)
БАССЕ Пауль-Вернер ФОН
Томас ШАЙТЕР (DE)
Томас ШАЙТЕР
Original Assignee
Инфинеон Текнолоджиз Аг (De)
Инфинеон Текнолоджиз Аг
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Инфинеон Текнолоджиз Аг (De), Инфинеон Текнолоджиз Аг filed Critical Инфинеон Текнолоджиз Аг (De)
Application granted granted Critical
Publication of RU2195048C2 publication Critical patent/RU2195048C2/ru
Publication of RU2001103636A publication Critical patent/RU2001103636A/ru

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Formation Of Insulating Films (AREA)
  • Measurement Of The Respiration, Hearing Ability, Form, And Blood Characteristics Of Living Organisms (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Image Input (AREA)
  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
  • Investigating Or Analyzing Materials By The Use Of Fluid Adsorption Or Reactions (AREA)

Claims (4)

1. Полупроводниковый компонент с полупроводниковым основанием (1), на котором размещен структурированный с промежутками слой (5) и в котором имеется пассивирующий слой, состоящий по меньшей мере из двух нанесенных один на другой пассивирующих двойных слоев (6, 7; 8, 9), покрывающий структурированный слой (5) со стороны, внешней по отношению к полупроводниковому основанию (1), и заполняющий промежутки в структурированном слое, каждый пассивирующий двойной слой сформирован из двух пассивирующих слоев, состоящих из различных диэлектрических материалов, и по меньшей мере пассивирующий двойной слой (8, 9), наиболее удаленный от полупроводникового основания, нанесен с равномерной толщиной на выровненную верхнюю сторону предыдущего пассивирующего двойного слоя.
2. Компонент по п.1, отличающийся тем, что пассивирующий двойной слой (6, 7) содержит пассивирующий слой из оксида (6) и пассивирующий слой из нитрида (7).
3. Компонент по п.2 или 3, отличающийся тем, что структурированный слой (5) представляет собой слой металлизации, нанесенный по меньшей мере на один слой из диэлектрика на верхней стороне полупроводникового основания (1).
4. Компонент по п.3, отличающийся тем, что слой металлизации образует проводящие плоскости емкостного измерительного датчика отпечатков пальцев, причем наиболее удаленный от слоя металлизации пассивирующий двойной слой (8, 9) имеет верхнюю плоскость, которая образует опорную плоскость для кончика пальца.
RU2001103636/28A 1998-07-09 1999-07-01 Полупроводниковый компонент с пассивирующим слоем RU2195048C2 (ru)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19830832.9 1998-07-09
DE19830832 1998-07-09

Publications (2)

Publication Number Publication Date
RU2195048C2 RU2195048C2 (ru) 2002-12-20
RU2001103636A true RU2001103636A (ru) 2004-03-20

Family

ID=7873546

Family Applications (1)

Application Number Title Priority Date Filing Date
RU2001103636/28A RU2195048C2 (ru) 1998-07-09 1999-07-01 Полупроводниковый компонент с пассивирующим слоем

Country Status (9)

Country Link
US (1) US6664612B2 (ru)
EP (1) EP1103031A1 (ru)
JP (1) JP3527708B2 (ru)
KR (1) KR100413860B1 (ru)
CN (1) CN1135493C (ru)
BR (1) BR9911980A (ru)
RU (1) RU2195048C2 (ru)
UA (1) UA46173C2 (ru)
WO (1) WO2000003345A1 (ru)

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US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6440814B1 (en) * 1998-12-30 2002-08-27 Stmicroelectronics, Inc. Electrostatic discharge protection for sensors
US6603192B2 (en) * 1999-07-30 2003-08-05 Stmicroelectronics, Inc. Scratch resistance improvement by filling metal gaps
DE50011685D1 (de) 2000-04-14 2005-12-29 Infineon Technologies Ag Kapazitiver biometrischer Sensor
US6759275B1 (en) 2001-09-04 2004-07-06 Megic Corporation Method for making high-performance RF integrated circuits
KR100449249B1 (ko) * 2001-12-26 2004-09-18 주식회사 하이닉스반도체 지문 인식 소자의 제조 방법
KR20040012294A (ko) * 2002-08-02 2004-02-11 삼성에스디아이 주식회사 지문 인식 센서를 구비한 터치 패널 장치
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US7355282B2 (en) 2004-09-09 2008-04-08 Megica Corporation Post passivation interconnection process and structures
US8384189B2 (en) 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
CN1901163B (zh) 2005-07-22 2011-04-13 米辑电子股份有限公司 连续电镀制作线路组件的方法及线路组件结构
JP5098276B2 (ja) * 2006-09-29 2012-12-12 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4833031B2 (ja) * 2006-11-06 2011-12-07 富士通セミコンダクター株式会社 表面形状センサとその製造方法
US8749021B2 (en) 2006-12-26 2014-06-10 Megit Acquisition Corp. Voltage regulator integrated with semiconductor chip
KR101113145B1 (ko) * 2007-04-05 2012-03-13 후지쯔 세미컨덕터 가부시키가이샤 표면 형상 센서와 그 제조 방법
CN100594591C (zh) * 2007-10-17 2010-03-17 中国科学院微电子研究所 一种提高氮化镓基场效应晶体管性能的方法
WO2010075447A1 (en) * 2008-12-26 2010-07-01 Megica Corporation Chip packages with power management integrated circuits and related techniques
US9812338B2 (en) * 2013-03-14 2017-11-07 Cree, Inc. Encapsulation of advanced devices using novel PECVD and ALD schemes
US9991399B2 (en) 2012-10-04 2018-06-05 Cree, Inc. Passivation structure for semiconductor devices
US8994073B2 (en) 2012-10-04 2015-03-31 Cree, Inc. Hydrogen mitigation schemes in the passivation of advanced devices
CN104201115A (zh) * 2014-09-12 2014-12-10 苏州晶方半导体科技股份有限公司 晶圆级指纹识别芯片封装结构及封装方法
CN106904568B (zh) * 2015-12-23 2019-06-28 中芯国际集成电路制造(上海)有限公司 一种mems器件及其制备方法、电子装置

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JPH01207932A (ja) 1988-02-16 1989-08-21 Fuji Electric Co Ltd 半導体装置
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Also Published As

Publication number Publication date
US6664612B2 (en) 2003-12-16
BR9911980A (pt) 2001-03-27
EP1103031A1 (de) 2001-05-30
CN1135493C (zh) 2004-01-21
JP3527708B2 (ja) 2004-05-17
RU2195048C2 (ru) 2002-12-20
KR20010071808A (ko) 2001-07-31
WO2000003345A1 (de) 2000-01-20
UA46173C2 (uk) 2002-05-15
CN1308751A (zh) 2001-08-15
KR100413860B1 (ko) 2004-01-07
US20010019168A1 (en) 2001-09-06
JP2002520841A (ja) 2002-07-09

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MM4A The patent is invalid due to non-payment of fees

Effective date: 20070702