NO20024196L - Fremgangsmåte for å lage en integrert kretspakke på en silikonskive - Google Patents
Fremgangsmåte for å lage en integrert kretspakke på en silikonskiveInfo
- Publication number
- NO20024196L NO20024196L NO20024196A NO20024196A NO20024196L NO 20024196 L NO20024196 L NO 20024196L NO 20024196 A NO20024196 A NO 20024196A NO 20024196 A NO20024196 A NO 20024196A NO 20024196 L NO20024196 L NO 20024196L
- Authority
- NO
- Norway
- Prior art keywords
- making
- integrated circuit
- circuit package
- silicone wafer
- wafer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 229920001296 polysiloxane Polymers 0.000 title 1
Classifications
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Manufacturing & Machinery (AREA)
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/558,396 US6281046B1 (en) | 2000-04-25 | 2000-04-25 | Method of forming an integrated circuit package at a wafer level |
PCT/US2001/011035 WO2001082361A2 (en) | 2000-04-25 | 2001-04-04 | Method of forming an integrated circuit package at a wafer level |
Publications (2)
Publication Number | Publication Date |
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NO20024196D0 NO20024196D0 (no) | 2002-09-03 |
NO20024196L true NO20024196L (no) | 2002-09-03 |
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NO20024196A NO20024196L (no) | 2000-04-25 | 2002-09-03 | Fremgangsmåte for å lage en integrert kretspakke på en silikonskive |
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US (1) | US6281046B1 (xx) |
EP (1) | EP1279193A2 (xx) |
JP (1) | JP2003532294A (xx) |
KR (1) | KR20040004761A (xx) |
CN (1) | CN1181524C (xx) |
AU (1) | AU2001249879A1 (xx) |
CA (1) | CA2402082A1 (xx) |
HK (1) | HK1053746A1 (xx) |
MY (1) | MY134243A (xx) |
NO (1) | NO20024196L (xx) |
TW (1) | TW503486B (xx) |
WO (1) | WO2001082361A2 (xx) |
Families Citing this family (75)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6506672B1 (en) * | 1999-06-30 | 2003-01-14 | University Of Maryland, College Park | Re-metallized aluminum bond pad, and method for making the same |
US6392428B1 (en) | 1999-11-16 | 2002-05-21 | Eaglestone Partners I, Llc | Wafer level interposer |
US6388335B1 (en) * | 1999-12-14 | 2002-05-14 | Atmel Corporation | Integrated circuit package formed at a wafer level |
EP1990833A3 (en) | 2000-02-25 | 2010-09-29 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
US6812048B1 (en) * | 2000-07-31 | 2004-11-02 | Eaglestone Partners I, Llc | Method for manufacturing a wafer-interposer assembly |
US6537831B1 (en) | 2000-07-31 | 2003-03-25 | Eaglestone Partners I, Llc | Method for selecting components for a matched set using a multi wafer interposer |
US6762502B1 (en) * | 2000-08-31 | 2004-07-13 | Micron Technology, Inc. | Semiconductor device packages including a plurality of layers substantially encapsulating leads thereof |
CN1901181B (zh) * | 2000-09-25 | 2012-09-05 | 揖斐电株式会社 | 半导体元件及其制造方法、多层印刷布线板及其制造方法 |
US6815712B1 (en) * | 2000-10-02 | 2004-11-09 | Eaglestone Partners I, Llc | Method for selecting components for a matched set from a wafer-interposer assembly |
US6686657B1 (en) | 2000-11-07 | 2004-02-03 | Eaglestone Partners I, Llc | Interposer for improved handling of semiconductor wafers and method of use of same |
US6580165B1 (en) * | 2000-11-16 | 2003-06-17 | Fairchild Semiconductor Corporation | Flip chip with solder pre-plated leadframe including locating holes |
US6529022B2 (en) * | 2000-12-15 | 2003-03-04 | Eaglestone Pareners I, Llc | Wafer testing interposer for a conventional package |
US6445075B1 (en) | 2001-01-26 | 2002-09-03 | Amkor Technology, Inc. | Semiconductor module package substrate |
US6494361B1 (en) * | 2001-01-26 | 2002-12-17 | Amkor Technology, Inc. | Semiconductor module package substrate fabrication method |
US6673653B2 (en) | 2001-02-23 | 2004-01-06 | Eaglestone Partners I, Llc | Wafer-interposer using a ceramic substrate |
US7115986B2 (en) * | 2001-05-02 | 2006-10-03 | Micron Technology, Inc. | Flexible ball grid array chip scale packages |
US7071024B2 (en) | 2001-05-21 | 2006-07-04 | Intel Corporation | Method for packaging a microelectronic device using on-die bond pad expansion |
US6586276B2 (en) * | 2001-07-11 | 2003-07-01 | Intel Corporation | Method for fabricating a microelectronic device using wafer-level adhesion layer deposition |
SG122743A1 (en) * | 2001-08-21 | 2006-06-29 | Micron Technology Inc | Microelectronic devices and methods of manufacture |
EP2273544A3 (en) * | 2001-12-14 | 2011-10-26 | STMicroelectronics S.r.l. | Semiconductor electronic device and method of manufacturing thereof |
SG104293A1 (en) * | 2002-01-09 | 2004-06-21 | Micron Technology Inc | Elimination of rdl using tape base flip chip on flex for die stacking |
US20030132513A1 (en) * | 2002-01-11 | 2003-07-17 | Motorola, Inc. | Semiconductor package device and method |
TW533521B (en) * | 2002-02-27 | 2003-05-21 | Advanced Semiconductor Eng | Solder ball process |
US6975035B2 (en) * | 2002-03-04 | 2005-12-13 | Micron Technology, Inc. | Method and apparatus for dielectric filling of flip chip on interposer assembly |
SG115456A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Semiconductor die packages with recessed interconnecting structures and methods for assembling the same |
SG111935A1 (en) | 2002-03-04 | 2005-06-29 | Micron Technology Inc | Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods |
SG115459A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Flip chip packaging using recessed interposer terminals |
SG121707A1 (en) | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
KR100455387B1 (ko) * | 2002-05-17 | 2004-11-06 | 삼성전자주식회사 | 반도체 칩의 범프의 제조방법과 이를 이용한 cog 패키지 |
US7358618B2 (en) * | 2002-07-15 | 2008-04-15 | Rohm Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20040036170A1 (en) * | 2002-08-20 | 2004-02-26 | Lee Teck Kheng | Double bumping of flexible substrate for first and second level interconnects |
US20050194665A1 (en) * | 2003-01-21 | 2005-09-08 | Huang Chien P. | Semiconductor package free of substrate and fabrication method thereof |
US6921860B2 (en) * | 2003-03-18 | 2005-07-26 | Micron Technology, Inc. | Microelectronic component assemblies having exposed contacts |
US6972152B2 (en) * | 2003-06-27 | 2005-12-06 | Intel Corporation | Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same |
TWI236113B (en) * | 2003-08-28 | 2005-07-11 | Advanced Semiconductor Eng | Semiconductor chip package and method for making the same |
US20050077603A1 (en) * | 2003-10-08 | 2005-04-14 | Dylan Yu | Method and structure for a wafer level packaging |
US7073702B2 (en) * | 2003-10-17 | 2006-07-11 | International Business Machines Corporation | Self-locking wire bond structure and method of making the same |
US7229933B2 (en) * | 2004-03-31 | 2007-06-12 | Intel Corporation | Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor |
US7253089B2 (en) * | 2004-06-14 | 2007-08-07 | Micron Technology, Inc. | Microfeature devices and methods for manufacturing microfeature devices |
US20060019468A1 (en) * | 2004-07-21 | 2006-01-26 | Beatty John J | Method of manufacturing a plurality of electronic assemblies |
US7524351B2 (en) | 2004-09-30 | 2009-04-28 | Intel Corporation | Nano-sized metals and alloys, and methods of assembling packages containing same |
US7495462B2 (en) * | 2005-03-24 | 2009-02-24 | Memsic, Inc. | Method of wafer-level packaging using low-aspect ratio through-wafer holes |
JP2007103462A (ja) * | 2005-09-30 | 2007-04-19 | Oki Electric Ind Co Ltd | 端子パッドと半田の接合構造、当該接合構造を有する半導体装置、およびその半導体装置の製造方法 |
CN100437958C (zh) * | 2005-11-03 | 2008-11-26 | 台湾应解股份有限公司 | 芯片封装结构及其制造方法 |
KR100665288B1 (ko) * | 2005-11-15 | 2007-01-09 | 삼성전기주식회사 | 플립칩 패키지 제조방법 |
CN100434354C (zh) * | 2006-04-07 | 2008-11-19 | 美新半导体(无锡)有限公司 | 具有y形通孔的圆片级气密性封装工艺 |
WO2007115371A1 (en) * | 2006-04-10 | 2007-10-18 | Epitactix Pty Ltd | Method, apparatus and resulting structures in the manufacture of semiconductors |
US20080060838A1 (en) * | 2006-09-13 | 2008-03-13 | Phoenix Precision Technology Corporation | Flip chip substrate structure and the method for manufacturing the same |
US7662665B2 (en) * | 2007-01-22 | 2010-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging |
JP2008211125A (ja) * | 2007-02-28 | 2008-09-11 | Spansion Llc | 半導体装置およびその製造方法 |
SG148056A1 (en) | 2007-05-17 | 2008-12-31 | Micron Technology Inc | Integrated circuit packages, methods of forming integrated circuit packages, and methods of assembling intgrated circuit packages |
US7982137B2 (en) * | 2007-06-27 | 2011-07-19 | Hamilton Sundstrand Corporation | Circuit board with an attached die and intermediate interposer |
KR101349373B1 (ko) * | 2007-07-31 | 2014-01-10 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
KR100974244B1 (ko) * | 2008-06-12 | 2010-08-05 | 엘지이노텍 주식회사 | 반도체 패키지 기판 및 반도체 패키지 기판의 제조방법 |
WO2010047006A1 (ja) * | 2008-10-23 | 2010-04-29 | パナソニック株式会社 | 半導体装置およびその製造方法 |
TWI387067B (zh) * | 2009-03-17 | 2013-02-21 | Chipmos Technologies Inc | 無基板晶片封裝及其製造方法 |
US8397380B2 (en) * | 2009-06-01 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling warpage in BGA components in a re-flow process |
US8278733B2 (en) * | 2009-08-25 | 2012-10-02 | Mediatek Inc. | Bonding pad structure and integrated circuit chip using such bonding pad structure |
US20110156260A1 (en) * | 2009-12-28 | 2011-06-30 | Yu-Hua Huang | Pad structure and integrated circuit chip with such pad structure |
GB2477358A (en) * | 2010-02-02 | 2011-08-03 | Thales Holdings Uk Plc | RF testing an integrated circuit assembly during manufacture using a interposed adaptor layer which is removed after test to attach the IC to a BGA |
US8574960B2 (en) * | 2010-02-03 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material |
CN102315186A (zh) * | 2010-06-30 | 2012-01-11 | 万国半导体股份有限公司 | 一种通过印刷粘接材料封装的半导体器件及其制造方法 |
WO2013012587A2 (en) | 2011-07-15 | 2013-01-24 | 3M Innovative Properties Company | Semiconductor package resin composition and usage method thereof |
US8928114B2 (en) * | 2012-01-17 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-assembly via modules and methods for forming the same |
US9258922B2 (en) | 2012-01-18 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | PoP structures including through-assembly via modules |
US20130234344A1 (en) * | 2012-03-06 | 2013-09-12 | Triquint Semiconductor, Inc. | Flip-chip packaging techniques and configurations |
US9613917B2 (en) | 2012-03-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package (PoP) device with integrated passive device in a via |
US9165887B2 (en) | 2012-09-10 | 2015-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with discrete blocks |
US8975726B2 (en) | 2012-10-11 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | POP structures and methods of forming the same |
US9391041B2 (en) | 2012-10-19 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out wafer level package structure |
US9679839B2 (en) | 2013-10-30 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip on package structure and method |
US9373527B2 (en) | 2013-10-30 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip on package structure and method |
TWI501549B (zh) * | 2013-12-11 | 2015-09-21 | Kuan Jung Chung | Method for forming cavity of surface acoustic wave element |
US10163773B1 (en) | 2017-08-11 | 2018-12-25 | General Electric Company | Electronics package having a self-aligning interconnect assembly and method of making same |
WO2020000414A1 (en) * | 2018-06-29 | 2020-01-02 | Intel Corporation | Coupling mechanisms for substrates, semiconductor packages, and/or printed circuit boards |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5504035A (en) | 1989-08-28 | 1996-04-02 | Lsi Logic Corporation | Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate |
US5468681A (en) | 1989-08-28 | 1995-11-21 | Lsi Logic Corporation | Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias |
US7041771B1 (en) * | 1995-08-11 | 2006-05-09 | Kac Holdings, Inc. | Encapsulant with fluxing properties and method of use in flip-chip surface mount reflow soldering |
US5851845A (en) | 1995-12-18 | 1998-12-22 | Micron Technology, Inc. | Process for packaging a semiconductor die using dicing and testing |
US6020220A (en) * | 1996-07-09 | 2000-02-01 | Tessera, Inc. | Compliant semiconductor chip assemblies and methods of making same |
US5604160A (en) | 1996-07-29 | 1997-02-18 | Motorola, Inc. | Method for packaging semiconductor devices |
US5798557A (en) | 1996-08-29 | 1998-08-25 | Harris Corporation | Lid wafer bond packaging and micromachining |
KR100222299B1 (ko) | 1996-12-16 | 1999-10-01 | 윤종용 | 웨이퍼 레벨 칩 스케일 패키지 및 그의 제조 방법 |
DE19702186C2 (de) * | 1997-01-23 | 2002-06-27 | Fraunhofer Ges Forschung | Verfahren zur Gehäusung von integrierten Schaltkreisen |
US6020637A (en) * | 1997-05-07 | 2000-02-01 | Signetics Kp Co., Ltd. | Ball grid array semiconductor package |
WO1999004430A1 (en) * | 1997-07-21 | 1999-01-28 | Aguila Technologies, Inc. | Semiconductor flip-chip package and method for the fabrication thereof |
JPH11214421A (ja) * | 1997-10-13 | 1999-08-06 | Matsushita Electric Ind Co Ltd | 半導体素子の電極形成方法 |
JP2000036518A (ja) * | 1998-07-16 | 2000-02-02 | Nitto Denko Corp | ウェハスケールパッケージ構造およびこれに用いる回路基板 |
US6388335B1 (en) * | 1999-12-14 | 2002-05-14 | Atmel Corporation | Integrated circuit package formed at a wafer level |
-
2000
- 2000-04-25 US US09/558,396 patent/US6281046B1/en not_active Expired - Fee Related
-
2001
- 2001-04-04 KR KR1020027013911A patent/KR20040004761A/ko not_active Application Discontinuation
- 2001-04-04 CN CNB018084257A patent/CN1181524C/zh not_active Expired - Fee Related
- 2001-04-04 WO PCT/US2001/011035 patent/WO2001082361A2/en active Application Filing
- 2001-04-04 AU AU2001249879A patent/AU2001249879A1/en not_active Abandoned
- 2001-04-04 CA CA002402082A patent/CA2402082A1/en not_active Abandoned
- 2001-04-04 JP JP2001579352A patent/JP2003532294A/ja not_active Withdrawn
- 2001-04-04 EP EP01923160A patent/EP1279193A2/en not_active Withdrawn
- 2001-04-17 MY MYPI20011821A patent/MY134243A/en unknown
- 2001-04-20 TW TW090109512A patent/TW503486B/zh active
-
2002
- 2002-09-03 NO NO20024196A patent/NO20024196L/no not_active Application Discontinuation
-
2003
- 2003-08-20 HK HK03105947A patent/HK1053746A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
WO2001082361A2 (en) | 2001-11-01 |
CN1181524C (zh) | 2004-12-22 |
JP2003532294A (ja) | 2003-10-28 |
HK1053746A1 (en) | 2003-10-31 |
AU2001249879A1 (en) | 2001-11-07 |
NO20024196D0 (no) | 2002-09-03 |
EP1279193A2 (en) | 2003-01-29 |
TW503486B (en) | 2002-09-21 |
WO2001082361A3 (en) | 2002-05-16 |
MY134243A (en) | 2007-11-30 |
US6281046B1 (en) | 2001-08-28 |
CN1426599A (zh) | 2003-06-25 |
CA2402082A1 (en) | 2001-11-01 |
KR20040004761A (ko) | 2004-01-14 |
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