NL194178C - Halfgeleidergeheugeneenheid. - Google Patents

Halfgeleidergeheugeneenheid. Download PDF

Info

Publication number
NL194178C
NL194178C NL9000431A NL9000431A NL194178C NL 194178 C NL194178 C NL 194178C NL 9000431 A NL9000431 A NL 9000431A NL 9000431 A NL9000431 A NL 9000431A NL 194178 C NL194178 C NL 194178C
Authority
NL
Netherlands
Prior art keywords
lines
word line
word
line
coupling
Prior art date
Application number
NL9000431A
Other languages
English (en)
Dutch (nl)
Other versions
NL194178B (nl
NL9000431A (nl
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of NL9000431A publication Critical patent/NL9000431A/nl
Publication of NL194178B publication Critical patent/NL194178B/xx
Application granted granted Critical
Publication of NL194178C publication Critical patent/NL194178C/nl

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/14Word line organisation; Word line lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225Shielding layers formed together with wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
NL9000431A 1989-12-29 1990-02-22 Halfgeleidergeheugeneenheid. NL194178C (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR890020102 1989-12-29
KR1019890020102A KR930001737B1 (ko) 1989-12-29 1989-12-29 반도체 메모리 어레이의 워드라인 배열방법

Publications (3)

Publication Number Publication Date
NL9000431A NL9000431A (nl) 1991-07-16
NL194178B NL194178B (nl) 2001-04-02
NL194178C true NL194178C (nl) 2001-08-03

Family

ID=19294143

Family Applications (1)

Application Number Title Priority Date Filing Date
NL9000431A NL194178C (nl) 1989-12-29 1990-02-22 Halfgeleidergeheugeneenheid.

Country Status (9)

Country Link
US (1) US5155700A (de)
JP (1) JPH0783060B2 (de)
KR (1) KR930001737B1 (de)
CN (1) CN1021997C (de)
DE (1) DE4005992C2 (de)
FR (1) FR2656726B1 (de)
GB (1) GB2239556B (de)
IT (1) IT1241524B (de)
NL (1) NL194178C (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0713864B2 (ja) * 1989-09-27 1995-02-15 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
JPH03171662A (ja) * 1989-11-29 1991-07-25 Sharp Corp 信号線システム
JPH04271086A (ja) * 1991-02-27 1992-09-28 Nec Corp 半導体集積回路
US5297094A (en) * 1991-07-17 1994-03-22 Sgs-Thomson Microelectronics, Inc. Integrated circuit memory device with redundant rows
US5311477A (en) * 1991-07-17 1994-05-10 Sgs-Thomson Microelectronics, Inc. Integrated circuit memory device having flash clear
US5287322A (en) * 1991-07-17 1994-02-15 Sgs-Thomson Microelectronics, Inc. Integrated circuit dual-port memory device having reduced capacitance
JP2000340766A (ja) * 1999-05-31 2000-12-08 Fujitsu Ltd 半導体記憶装置
US6327170B1 (en) * 1999-09-28 2001-12-04 Infineon Technologies Ag Reducing impact of coupling noise in multi-level bitline architecture
US6567329B2 (en) * 2001-08-28 2003-05-20 Intel Corporation Multiple word-line accessing and accessor
US6563727B1 (en) * 2002-07-31 2003-05-13 Alan Roth Method and structure for reducing noise effects in content addressable memories
US7244995B2 (en) * 2004-10-18 2007-07-17 Texas Instruments Incorporated Scrambling method to reduce wordline coupling noise
US7952901B2 (en) * 2007-08-09 2011-05-31 Qualcomm Incorporated Content addressable memory
US20090154215A1 (en) * 2007-12-14 2009-06-18 Spansion Llc Reducing noise and disturbance between memory storage elements using angled wordlines
JP5612803B2 (ja) * 2007-12-25 2014-10-22 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. 半導体記憶装置
US8411479B2 (en) * 2009-07-23 2013-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuits, systems, and methods for routing the memory circuits
CN113270130A (zh) * 2020-05-29 2021-08-17 台湾积体电路制造股份有限公司 存储器设备

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57208691A (en) * 1981-06-15 1982-12-21 Mitsubishi Electric Corp Semiconductor memory
JPS59124092A (ja) * 1982-12-29 1984-07-18 Fujitsu Ltd メモリ装置
US4729119A (en) * 1984-05-21 1988-03-01 General Computer Corporation Apparatus and methods for processing data through a random access memory system
US4733374A (en) * 1985-03-30 1988-03-22 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device
CA1305255C (en) * 1986-08-25 1992-07-14 Joseph Lebowitz Marching interconnecting lines in semiconductor integrated circuits
JPS63153792A (ja) * 1986-12-17 1988-06-27 Sharp Corp 半導体メモリ装置
JPH0713858B2 (ja) * 1988-08-30 1995-02-15 三菱電機株式会社 半導体記憶装置

Also Published As

Publication number Publication date
IT1241524B (it) 1994-01-17
GB2239556B (en) 1993-08-25
CN1021997C (zh) 1993-09-01
IT9048189A0 (it) 1990-07-31
KR910013262A (ko) 1991-08-08
JPH0783060B2 (ja) 1995-09-06
US5155700A (en) 1992-10-13
GB2239556A (en) 1991-07-03
NL194178B (nl) 2001-04-02
FR2656726B1 (fr) 1995-02-03
DE4005992C2 (de) 1994-01-27
NL9000431A (nl) 1991-07-16
CN1052967A (zh) 1991-07-10
DE4005992A1 (de) 1991-07-11
IT9048189A1 (it) 1992-01-31
GB9004448D0 (en) 1990-04-25
FR2656726A1 (fr) 1991-07-05
KR930001737B1 (ko) 1993-03-12
JPH03203369A (ja) 1991-09-05

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Legal Events

Date Code Title Description
A1A A request for search or an international-type search has been filed
BB A search report has been drawn up
BC A request for examination has been filed
V4 Discontinued because of reaching the maximum lifetime of a patent

Effective date: 20100222