MY134327A - Process for creating holes in polymeric substrates - Google Patents

Process for creating holes in polymeric substrates

Info

Publication number
MY134327A
MY134327A MYPI20032397A MYPI20032397A MY134327A MY 134327 A MY134327 A MY 134327A MY PI20032397 A MYPI20032397 A MY PI20032397A MY PI20032397 A MYPI20032397 A MY PI20032397A MY 134327 A MY134327 A MY 134327A
Authority
MY
Malaysia
Prior art keywords
curable
film
curable film
resist
polymeric substrates
Prior art date
Application number
MYPI20032397A
Other languages
English (en)
Inventor
Kevin C Olson
Alan E Wang
Original Assignee
Ppg Ind Ohio Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ppg Ind Ohio Inc filed Critical Ppg Ind Ohio Inc
Publication of MY134327A publication Critical patent/MY134327A/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12361—All metal or with adjacent metals having aperture or cut
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24322—Composite web or sheet

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Materials For Photolithography (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Paints Or Removers (AREA)
MYPI20032397A 2002-06-27 2003-06-26 Process for creating holes in polymeric substrates MY134327A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/183,674 US6824959B2 (en) 2002-06-27 2002-06-27 Process for creating holes in polymeric substrates

Publications (1)

Publication Number Publication Date
MY134327A true MY134327A (en) 2007-12-31

Family

ID=29779180

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI20032397A MY134327A (en) 2002-06-27 2003-06-26 Process for creating holes in polymeric substrates

Country Status (11)

Country Link
US (1) US6824959B2 (enExample)
EP (1) EP1523868B1 (enExample)
JP (3) JP4411410B2 (enExample)
KR (1) KR100659808B1 (enExample)
CN (1) CN1672472A (enExample)
AU (1) AU2003245746A1 (enExample)
DE (1) DE60317902T2 (enExample)
ES (1) ES2297175T3 (enExample)
MY (1) MY134327A (enExample)
TW (1) TWI228953B (enExample)
WO (1) WO2004004430A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050153107A1 (en) * 2004-01-12 2005-07-14 Tdk Corporation Substrate having functional layer pattern formed thereon and method of forming functional layer pattern
EP1861857A4 (en) * 2004-12-07 2009-09-02 Multi Fineline Electronix Inc MINIATURE CIRCUITS AND INDUCTIVE COMPONENTS AND MANUFACTURING METHOD THEREFOR
KR100738055B1 (ko) * 2005-05-18 2007-07-12 삼성에스디아이 주식회사 전자소자의 적층 형성 방법 및 이를 이용한 ｆｅｄ의제조방법
US8008188B2 (en) * 2007-06-11 2011-08-30 Ppg Industries Ohio, Inc. Method of forming solid blind vias through the dielectric coating on high density interconnect substrate materials
US8637778B2 (en) * 2010-04-08 2014-01-28 Intel Corporation Debond interconnect structures

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FR2041471A5 (en) 1969-04-25 1971-01-29 Cii Multi-layer circuits with thermosetting - dielectric
US3984299A (en) 1970-06-19 1976-10-05 Ppg Industries, Inc. Process for electrodepositing cationic compositions
US3738835A (en) 1971-10-21 1973-06-12 Ibm Electrophoretic photoresist composition and a method of forming etch resistant masks
US3947338A (en) 1971-10-28 1976-03-30 Ppg Industries, Inc. Method of electrodepositing self-crosslinking cationic compositions
US3793278A (en) 1972-03-10 1974-02-19 Ppg Industries Inc Method of preparing sulfonium group containing compositions
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DE2707405C3 (de) 1976-07-19 1987-12-03 Vianova Kunstharz Ag, Werndorf Verfahren zur Herstellung von Bindemitteln für die Elektrotauchlackierung
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Also Published As

Publication number Publication date
DE60317902T2 (de) 2008-10-23
KR100659808B1 (ko) 2006-12-19
AU2003245746A1 (en) 2004-01-19
WO2004004430A1 (en) 2004-01-08
JP2005531162A (ja) 2005-10-13
EP1523868A1 (en) 2005-04-20
KR20050006301A (ko) 2005-01-15
US20040000426A1 (en) 2004-01-01
JP2010118708A (ja) 2010-05-27
JP4411410B2 (ja) 2010-02-10
DE60317902D1 (de) 2008-01-17
JP2007027786A (ja) 2007-02-01
EP1523868B1 (en) 2007-12-05
TW200414848A (en) 2004-08-01
TWI228953B (en) 2005-03-01
US6824959B2 (en) 2004-11-30
CN1672472A (zh) 2005-09-21
ES2297175T3 (es) 2008-05-01

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