MXPA01013012A - Matriz y/o paquete de circuito integrado que tiene un arreglo de contacto de separacion variable para la maximizacion del numero de lineas de senal por capa de encaminamiento. - Google Patents

Matriz y/o paquete de circuito integrado que tiene un arreglo de contacto de separacion variable para la maximizacion del numero de lineas de senal por capa de encaminamiento.

Info

Publication number
MXPA01013012A
MXPA01013012A MXPA01013012A MXPA01013012A MXPA01013012A MX PA01013012 A MXPA01013012 A MX PA01013012A MX PA01013012 A MXPA01013012 A MX PA01013012A MX PA01013012 A MXPA01013012 A MX PA01013012A MX PA01013012 A MXPA01013012 A MX PA01013012A
Authority
MX
Mexico
Prior art keywords
electrical connections
connections
distance
integrated circuit
contacts
Prior art date
Application number
MXPA01013012A
Other languages
English (en)
Spanish (es)
Inventor
Bidyut K Bhattacharyya
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of MXPA01013012A publication Critical patent/MXPA01013012A/es

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
MXPA01013012A 1999-06-29 2000-05-26 Matriz y/o paquete de circuito integrado que tiene un arreglo de contacto de separacion variable para la maximizacion del numero de lineas de senal por capa de encaminamiento. MXPA01013012A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/342,550 US6664620B2 (en) 1999-06-29 1999-06-29 Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
PCT/US2000/014904 WO2001001487A1 (en) 1999-06-29 2000-05-26 Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer

Publications (1)

Publication Number Publication Date
MXPA01013012A true MXPA01013012A (es) 2004-10-15

Family

ID=23342320

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA01013012A MXPA01013012A (es) 1999-06-29 2000-05-26 Matriz y/o paquete de circuito integrado que tiene un arreglo de contacto de separacion variable para la maximizacion del numero de lineas de senal por capa de encaminamiento.

Country Status (7)

Country Link
US (2) US6664620B2 (enExample)
JP (1) JP2003529203A (enExample)
KR (1) KR20020016867A (enExample)
CN (1) CN1225023C (enExample)
AU (1) AU5867800A (enExample)
MX (1) MXPA01013012A (enExample)
WO (1) WO2001001487A1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6664620B2 (en) 1999-06-29 2003-12-16 Intel Corporation Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
US20040212103A1 (en) * 2000-06-19 2004-10-28 Herman Kwong Techniques for pin arrangements in circuit chips
US6885102B2 (en) * 2002-08-26 2005-04-26 Intel Corporation Electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts
JP3780996B2 (ja) * 2002-10-11 2006-05-31 セイコーエプソン株式会社 回路基板、バンプ付き半導体素子の実装構造、バンプ付き半導体素子の実装方法、電気光学装置、並びに電子機器
US20050073805A1 (en) * 2003-09-19 2005-04-07 Brent Stone Integrated circuit package
DE102004010299B4 (de) * 2004-03-03 2008-03-06 Atmel Germany Gmbh Infrarot-Empfänger-Chip
KR100652549B1 (ko) * 2005-07-11 2006-12-01 삼성전기주식회사 다각형, 라운드 및 원형 플립칩 볼 그리드 어레이 기판
TWM339185U (en) * 2008-01-15 2008-08-21 Wintek Corp Bend prevention structure for connection terminal of FPC
CN101673725B (zh) * 2008-09-09 2011-02-09 奇景光电股份有限公司 可挠性电路板
USD639755S1 (en) * 2010-01-20 2011-06-14 Celadon Systems, Inc. Top contact layout board in an electrical system
USD639757S1 (en) * 2010-08-16 2011-06-14 Celadon Systems, Inc. Top contact layout board in an electrical system
KR20120118763A (ko) * 2011-04-19 2012-10-29 삼성전자주식회사 디램 패키지, 디램 패키지를 포함하는 디램 모듈, 디램 패키지를 포함하는 그래픽 모듈, 그리고 디램 패키지를 포함하는 멀티미디어 장치
WO2013177445A1 (en) 2012-05-23 2013-11-28 Massachusetts Institute Of Technology Grid arrays with enhanced fatigue life
USD722031S1 (en) * 2013-12-31 2015-02-03 Celadon Systems, Inc. Top contact layout board in an electrical system
KR102245132B1 (ko) * 2014-05-14 2021-04-28 삼성전자 주식회사 트레이스를 가지는 인쇄회로기판 및 볼 그리드 어레이 패키지
US10090251B2 (en) 2015-07-24 2018-10-02 Infineon Technologies Ag Semiconductor chip having a dense arrangement of contact terminals
US9846759B2 (en) * 2015-07-30 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Global connection routing method and system for performing the same
US20180047692A1 (en) 2016-08-10 2018-02-15 Amkor Technology, Inc. Method and System for Packing Optimization of Semiconductor Devices
US9799618B1 (en) 2016-10-12 2017-10-24 International Business Machines Corporation Mixed UBM and mixed pitch on a single die
CN110689910B (zh) * 2018-07-05 2024-10-11 森富科技股份有限公司 内存配置结构

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BE755950A (fr) * 1969-09-11 1971-03-09 Philips Nv Procede permettant d'etablir des liaisons electriques entre desemplacements de contact d'un corps semiconducteur et des conducteurs d'alimentation
US4495377A (en) * 1982-12-30 1985-01-22 International Business Machines Corporation Substrate wiring patterns for connecting to integrated-circuit chips
US4875138A (en) * 1986-10-20 1989-10-17 United Technologies Corporation Variable pitch IC bond pad arrangement
US5089881A (en) 1988-11-03 1992-02-18 Micro Substrates, Inc. Fine-pitch chip carrier
JP2626698B2 (ja) * 1989-06-15 1997-07-02 株式会社 グラフィコ 放射型・パラレル・システムバス
JP2872825B2 (ja) 1991-05-13 1999-03-24 三菱電機株式会社 半導体装置用パッケージ
JPH05160292A (ja) * 1991-06-06 1993-06-25 Toshiba Corp 多層パッケージ
US5729894A (en) 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
US5468994A (en) 1992-12-10 1995-11-21 Hewlett-Packard Company High pin count package for semiconductor device
JP2867313B2 (ja) * 1993-12-10 1999-03-08 日本特殊陶業株式会社 セラミック基板
US5463191A (en) 1994-03-14 1995-10-31 Dell Usa, L.P. Circuit board having an improved fine pitch ball grid array and method of assembly therefor
US5491364A (en) * 1994-08-31 1996-02-13 Delco Electronics Corporation Reduced stress terminal pattern for integrated circuit devices and packages
US5713744A (en) 1994-09-28 1998-02-03 The Whitaker Corporation Integrated circuit socket for ball grid array and land grid array lead styles
TW353223B (en) 1995-10-10 1999-02-21 Acc Microelectronics Corp Semiconductor board providing high signal pin utilization
US5702256A (en) 1995-12-28 1997-12-30 Intel Corporation Land grid array socket for use with integrated circuit modules of different sizes including modules which are larger than the socket
US5686764A (en) * 1996-03-20 1997-11-11 Lsi Logic Corporation Flip chip package with reduced number of package layers
US5952726A (en) * 1996-11-12 1999-09-14 Lsi Logic Corporation Flip chip bump distribution on die
US6310398B1 (en) * 1998-12-03 2001-10-30 Walter M. Katz Routable high-density interfaces for integrated circuit devices
US6664620B2 (en) 1999-06-29 2003-12-16 Intel Corporation Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer

Also Published As

Publication number Publication date
CN1225023C (zh) 2005-10-26
WO2001001487A1 (en) 2001-01-04
CN1359538A (zh) 2002-07-17
US20040061223A1 (en) 2004-04-01
US6664620B2 (en) 2003-12-16
JP2003529203A (ja) 2003-09-30
KR20020016867A (ko) 2002-03-06
US7030479B2 (en) 2006-04-18
AU5867800A (en) 2001-01-31
US20010045633A1 (en) 2001-11-29

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