MXPA01002814A - Peliculas delgadas ferroelectricas de tetragonalidad reducida. - Google Patents

Peliculas delgadas ferroelectricas de tetragonalidad reducida.

Info

Publication number
MXPA01002814A
MXPA01002814A MXPA01002814A MXPA01002814A MXPA01002814A MX PA01002814 A MXPA01002814 A MX PA01002814A MX PA01002814 A MXPA01002814 A MX PA01002814A MX PA01002814 A MXPA01002814 A MX PA01002814A MX PA01002814 A MXPA01002814 A MX PA01002814A
Authority
MX
Mexico
Prior art keywords
ferroelectric
cell
tetragonality
polarization
ferroelectric layer
Prior art date
Application number
MXPA01002814A
Other languages
English (en)
Spanish (es)
Inventor
Ramamoorthy Ramesh
Original Assignee
Telcordia Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telcordia Tech Inc filed Critical Telcordia Tech Inc
Publication of MXPA01002814A publication Critical patent/MXPA01002814A/es

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/516Insulating materials associated therewith with at least one ferroelectric layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
MXPA01002814A 1998-09-24 1999-09-24 Peliculas delgadas ferroelectricas de tetragonalidad reducida. MXPA01002814A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16077898A 1998-09-24 1998-09-24
PCT/US1999/022178 WO2000017936A1 (en) 1998-09-24 1999-09-24 Ferroelectric thin films of reduced tetragonality

Publications (1)

Publication Number Publication Date
MXPA01002814A true MXPA01002814A (es) 2002-04-08

Family

ID=22578406

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA01002814A MXPA01002814A (es) 1998-09-24 1999-09-24 Peliculas delgadas ferroelectricas de tetragonalidad reducida.

Country Status (10)

Country Link
EP (1) EP1127378A1 (zh)
JP (1) JP2002525876A (zh)
KR (1) KR20010075336A (zh)
CN (1) CN1319256A (zh)
AU (1) AU6161599A (zh)
CA (1) CA2343129A1 (zh)
ID (1) ID27451A (zh)
MX (1) MXPA01002814A (zh)
TW (1) TW445647B (zh)
WO (1) WO2000017936A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3791614B2 (ja) 2002-10-24 2006-06-28 セイコーエプソン株式会社 強誘電体膜、強誘電体メモリ装置、圧電素子、半導体素子、圧電アクチュエータ、液体噴射ヘッド及びプリンタ
JP2006024748A (ja) * 2004-07-08 2006-01-26 Fujitsu Ltd 強誘電体キャパシタをもつ半導体装置及びその製造方法
JP5103706B2 (ja) * 2004-07-30 2012-12-19 富士通株式会社 強誘電体キャパシタをもつ半導体装置及びその製造方法
JP4303209B2 (ja) 2005-02-04 2009-07-29 富士通株式会社 強誘電体素子及び強誘電体素子の製造方法
JP4257537B2 (ja) * 2005-06-02 2009-04-22 セイコーエプソン株式会社 強誘電体層の製造方法、電子機器の製造方法、強誘電体メモリ装置の製造方法、圧電素子の製造方法、およびインクジェット式記録ヘッドの製造方法
JP6036460B2 (ja) 2013-03-26 2016-11-30 三菱マテリアル株式会社 PNbZT強誘電体薄膜の形成方法
TWI739051B (zh) 2018-12-13 2021-09-11 財團法人工業技術研究院 鐵電記憶體
KR102293876B1 (ko) * 2019-12-10 2021-08-27 브이메모리 주식회사 변동 저저항 라인 기반 전자 소자 및 이의 제어 방법
TWI744784B (zh) 2020-02-03 2021-11-01 財團法人工業技術研究院 鐵電記憶體及其製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270298A (en) * 1992-03-05 1993-12-14 Bell Communications Research, Inc. Cubic metal oxide thin film epitaxially grown on silicon
US5248564A (en) * 1992-12-09 1993-09-28 Bell Communications Research, Inc. C-axis perovskite thin films grown on silicon dioxide
US5777356A (en) * 1996-01-03 1998-07-07 Bell Communications Research, Inc. Platinum-free ferroelectric memory cell with intermetallic barrier layer and method of making same

Also Published As

Publication number Publication date
WO2000017936A1 (en) 2000-03-30
ID27451A (id) 2001-04-12
CA2343129A1 (en) 2000-03-30
AU6161599A (en) 2000-04-10
KR20010075336A (ko) 2001-08-09
TW445647B (en) 2001-07-11
EP1127378A1 (en) 2001-08-29
CN1319256A (zh) 2001-10-24
JP2002525876A (ja) 2002-08-13

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