MXPA01002814A

MXPA01002814A - Ferroelectric thin films of reduced tetragonality.

Info

Publication number: MXPA01002814A
Application number: MXPA01002814A
Authority: MX
Inventors: Ramamoorthy Ramesh
Original assignee: Telcordia Tech Inc
Priority date: 1998-09-24
Filing date: 1999-09-24
Publication date: 2002-04-08
Also published as: WO2000017936A1; ID27451A; CA2343129A1; AU6161599A; KR20010075336A; TW445647B; EP1127378A1; CN1319256A; JP2002525876A

Abstract

A ferroelectric material, especially as incorporated into a crystallographically oriented epitaxial ferroelectric cell, of Pb1-xLaxZryTi1-yO3 or Pb1-xNbxZryTi1-yO3 having a moderately high La or Nb content such that the unit cell is less tetragonal, that is, more nearly cubic, so as to reduce stress effects. A most preferred value of the c/a constant is about 1.01. Exemplary compositional ranges for x are 6 to 20 % for La and 3 to 15 % for Nb, when y is 20 %. The reduced polarizabilities voltages are consistent with integrated ferrroelectric memories operating at 3.0V and lower.

Description

STRAIGHT REDUCED TETRAGONAL FERROELECTRIC FILMS FIELD OF THE INVENTION The invention relates generally to perovskite materials. In particular, the invention relates to ferroelectric materials useful in ferroelectric memory cells.

PREVIOUS ART Ferroelectric random access memories (FRAM) offer the possibility of a non-volatile memory to replace silicon memory, since FRAM does not require power to maintain its polarized state electrically. The general schematic structure of a FRAM 10 is illustrated in FIG. 1 and includes two capacitor plates 12, 14 between which a body 16 of ferroelectric material is placed. Not only the ferroelectric material 16 has a dielectric constant substantially in excess of the unit, but also under the appropriate conditions the ferroelectric material is bistable. Once the capacitor plates 12, 14 have polarized the ferroelectric material in the directed polarization state either up or down, the body Ref: 127756 of ferroelectric material 16 remains in that state even after the polarization voltage is removed. That is, a load (or voltage) remains in cell 10 without any energy being commonly applied. Time later, the load can be measured. In this way, the FRAM 10 forms a non-volatile memory. Conventionally, the FRAM has included a polycrystalline ferroelectric material placed in the middle of two electrodes in a capacitor structure. However, such design has suffered from problems of reliability and aging. More recently, Ramesh et al have been developing crystallographically oriented ferroelectric cells using metal oxide electrodes. Dhote et al. They have described a lower platinum-based electrode in U.S. Patent Application. Serial No. 08 / 578,499, filed December 26, 1995, not U.S. Pat. No. 5,798,903, also published as PCT Publication 97/23886 on July 3, 1997. An example of the structure of Dhote et al. For a ferroelectric random access memory (FRAM) 20, similar to a dynamic silicon RAM, it is illustrated in the cross section of FIG. 2. It is understood that this FRAM structure is replicated many times to form a large FRAM integrated circuit and that other support circuitry needs to be formed in the same chip. The structure of total FRAM, with few exceptions, is known and described by Ramesh in the U.S. patents and applications. previously cited. Kinney provides a good review of FRAM integrated circuits in "Signal magnitudes in high density ferroelectric memories", Integratec? ferroel ectri cs, vol. 4, 1994, pp. 131-144. The FRAM 20 is formed on a substrate 22 of oriented crystalline silicon (001) so that other silicon circuitry can be easily incorporated. A metal oxide semiconductor transistor (MOS) is formed by the diffusion or implantation of conductivity-type impurifiers opposite to that of the substrate 22 within the source and drainage wells 24, 26. The intervening gate region is covered with a structure of gate 28 including a lower gate oxide and a top metal gate line, eg aluminum, to control the gate. A first inter-level dielectric layer 30, for example of silicon dioxide, is deposited on the substrate 22 and the structure of the transistor. A contact hole 32 is lithographically recorded by the first intermediate level dielectric layer 30 over the source well 24, and is filled with polysilicon to form a polysilicon contact pin with the source of the transistor 24. A metallic line of the source 34 is delineated photolithographically on top of the first intermediate level dielectric layer 30 and electrically contacts the polysilicon plug 32. A second intermediate level dielectric layer 36 is then deposited on the first intermediate level dielectric layer 30. Another contact hole 38 is recorded through both the first and the second intermediate level dielectric layers., 36 over the area of the consumption well 26, and it is filled with polysilicon to form a contact with the socket of the transistor 26. Processing up to this point is very standard in silicon technology. A lightweight mask is then deposited and defined to have an opening over the contact contact hole 38, but of a larger area for the desired size of the capacitor, although in commercial manufacture a dry masked plasma etching would typically be performed. A sequence of layers is deposited on the mask and in the opening. A polysilicon layer 40 provides good electrical contact with the polysilicon plug 38. A layer of TiN 42 and a platinum layer 44 form conductive barrier layers between the polysilicon and the oxidizing metal-oxide contacts. Polysilicon is semiconductor, but if its surface is oxidized in Si02, a stable, insulating layer is formed that avoids electrical contact. On the platinum layer 44 is deposited a layer 46 of a conductive metal oxide, preferably a perovskite, such as lanthanum strontium strontium oxide (LSCO), although other metal oxides, especially layered perovskites, could be used. This material has a composition nominally given by La0 5Sr0 5CoO3, although compositions of approximately La1.xSrxCo03 with 0.15 >are possible; x = 0.85. It is now well known that the LSCO forms an acceptable electrical contact, and also promotes the highly oriented growth of perovskite ferroelectric materials. The photomask is then removed leaving the lower stack of layers 40, 42, 44, 46 shown in FIG. 2. Other photomasks are then defined by leaving the deposition according to a field oxide layer of form Z 48, which covers the sides of the previously defined lower stack, has a projection extending over the edge of the top surface of the stack lower, and has a foot that extends outward from the bottom of the bottom stack, but leaves a central opening for the ferroelectric stack later deposited. The field oxide layer 48 electrically insulates the ferroelectric material deposited later from the side portions of the lower electrode. In the past, the field oxide layer 48 had been formed of SiO2 or TiO2, but even these materials are not ideal. Perovskite ferroelectric materials when deposited on these materials tend to form a mixture of perovskite and pyrochlore phases, which then records differentially, resulting in unreliable etching. A better material for the field oxide layer 48 is bismuth titanate (approximately of the stoichiometric composition Bi4Ti3012), which is a perovskite and can grow by the same growth process as the other perovskite layers. Ramesh in U.S. Pat. 5,248,564 discloses that Bi4Ti3012 is a powerful mold layer for promoting the growth of crystallographically oriented perovskites on unoriented substrates, thus a field oxide layer Bi4Ti3012 48 ensures good quality of ferroelectric materials growing on it. Other perovskite materials could be substituted for bismuth titanate, as long as they are not highly conductive and display a low dielectric constant, e.g., without being a ferroelectric material. For most effective molds, the perovskite forms of Bi4Ti3012 should have a layered structure, that is, have a grid on the c axis that is at least twice that of the a and b axes. After the formation of the field oxide 48, another photomask is deposited and defined which includes an opening around the bottom stack 40, 42, 44, 46 but the outer periphery of its bottom covers the foot 49 of the oxide layer. field 48. A ferroelectric layer 50 is then deposited under conditions that favor crystallographically oriented growth. Preferably, the ferroelectric layer 50 comprises lead titanate lanthanum zirconium (PLZT) or lead titania niobium zirconium (PNZT). The deposition of the ferroelectric layer of perovskite on LSCO or other conductive electrodes similar to perovskite allow the ferroelectric material to be deposited at a relatively low temperature, but which still shows favorable crystallinity. On the ferroelectric material layer 50, an upper conductive metal oxide layer 52 is deposited, preferably symmetrically formed with the lower conductive metal oxide layer 44, of a perovskite, such as LSCO. An upper layer of platinum 54 is deposited on the upper layer of conductive metal oxide 52. This layer 54 is not considered to involve critical technology, and its platinum composition was selected only as an intermediate solution. It is anticipated that the composition will be changed to TiW or other common metallizations in silicon technology. After the top layer of platinum 54 is deposited, the photomask is removed leaving the structure of the top stack illustrated in FIG. 2. A third intermediate level dielectric layer 56 is deposited and recorded to cover the ferroelectric cell. This layer 56 projects more as a passivation layer than as an intermediate level dielectric. The upper electrode 54 is then electrically contacted, recording a path 60 through the third intermediate level dielectric layer 56., which covers the ferroelectric cell, which fills track 60 with Ti / W, and which delineates a metal capacitor line 62 from Al, which electrically contacts the Ti / W 60 plug. Dhote et al. They found that depositing the lower layer of platinum 44 at a relatively high temperature, in the vicinity of 500-550 ° C, allows the deposition of the ferroelectric pile (the ferroelectric material and the two layers of metal oxide forming layers) to a supply Higher thermal, which is defined as the integral temperature (measured in ° C) the time at which the sample is at that temperature. Since the three layers, that is, the PNZT 50 layer, the LSCO upper electrode 52 and the upper Pt layer 54, are typically deposited in a single chamber at a single temperature, the thermal supply becomes the product of the temperature of deposition and total deposition time. PNZT is a well-known ferroelectric material. Dhote et al. give particular examples of the composition of PNZT as Pb0-04Nb0-18Zr0 78Ti03 and PbNb0 04Zr0 28Ti0-68O3, ie PNZT which is on the one hand poor in lead and on the other hand rich in copper and rich in zirconium. A problem that needs to be addressed in ferroelectric memories of any kind is its fatigue behavior. It is generally observed that the ferroelectric or polarization properties of a ferroelectric cell suffer from deterioration in a large number of read-write cycles. The polycrystalline cells suffer greatly from fatigue while the crystallographically oriented cells exhibit much greater resistance to fatigue. However, fatigue is still believed to be a problem with cells that are oriented in a christological manner. In order to quantify fatigue and other operating characteristics in ferroelectric cells, it is necessary to understand the polarization characteristics of a ferroelectric cell. A cycle of ferroelectric hysteresis 64 is illustrated in FIG. 3. The horizontal axis represents the voltage across the cell. The vertical axis represents the polarization of the material, if it is printed immediately or is residual (remnant), that is, without a voltage that is applied. Polarization refers proportionally to the time integral of the load flowing to or from the cell. The hysteresis curve is highly non-linear. From this discussion, it is assumed that the characteristics are asymmetric although this is not usually true in practice. The hysteresis curve illustrated implies that the hysteresis curve approaches a maximum polarization Psat as the applied voltage approaches asymptotically at a saturation voltage Vsat. However, the polarization is usually performed along the voltage direction only for Vmax, which produces a Pmax of only about 90% Psat. The difference in the polarization difference between polarization to ± Vmax is indicated by P * = 2Pmax for a symmetric hysteresis curve. When the cell has been pressed to vma? with an accompanying polarization of Pmax, but then the voltage is reduced to V = 0, the polarization remains nevertheless to a residual polarization Pr. If the cell has been negatively polarized, the polarization is maintained in a negative residual polarization, which is equal to -Pr in the symmetric hysteresis curve. Assuming that the reading is made by positive polarization with an applied voltage of Vmax, the charge measured in the polarization corresponds to either a non-switched polarization P or a switched polarization P *. The reading circuit must be able to distinguish the difference between them, which is the pulsed polarization? P = P * - P "For a symmetric hysteresis curve, the pulsed polarization? P equals 2Pr. believes that for higher performance the hysteresis curve should be as rectangular as possible, that is, the coercive voltage Vc should be maximized for a given Vmax.This perception is based on the fact that the remaining polarization Pr should be made as large as possible. possible, and that the remaining polarization increases with the coercive voltage. However, it is believed that there are some considerations of the opposite effect. Another consideration is that if the ferroelectric memories are to be commercialized, they must be compatible with other silicon integrated circuits used in, for example, personal computers, computer work stations, and other computer controlled applications. For many years, digital silicon integrated circuits, either logical or memory, were supplied with power via a DC voltage Vco of 5VDC. However, in recent years, advanced integrated circuits have been designed to supply power through lower voltages, for example 3.0VDC, 2.3VDC and 1.8VDC. Decreased voltages reduce both the problems associated with thermal dissipation in extremely dense integrated circuits and also provide extended battery operation for laptops. An example of the critical reading circuitry associated with a ferroelectric cell 10 is illustrated in the circuit diagram of FIG. 4. This modality follows the description of Kynney et al. Other equivalent circuitry is possible. Associated with each ferroelectric cell 10 is a read transistor 66, which corresponds to the MOS transistor 23 of FIG. 2. A word line 68 controls the read transistors 66 of a column of memory cells 10, but in a direction orthogonal to the word line 68. The reading transistor 66 selectively connects the ferroelectric cell 10 to a line of bits 70, which is connected similarly to the row of memory cells 10. That is, the word lines 68 and lines of bits 70 run in perpendicular directions on a rectangular array of memory cells 10. Due to the effect of hysteresis on the material ferroelectric, it is necessary to provide during the reading pss the selective polarization of the other electrode of the ferroelectric cell 10 through a plate line 72, which runs in parallel to the word line 68. During the reading pss, the ferroelectric cell 10 is temporarily connected to the line of bits 70 and the load stored in cell 10, either in the positive or negative state, is shared with a capacitance para The larger amplifier 74 associated with the bit line 70, thus generating two possible voltages in the bit line 70. A sense amplifier 76 then compares this voltage to a reference voltage resulting from a charge stored in a reference capacitor 78. and enters the sense amplifier 76 on line 79. The sense amplifier 76 outputs a digital signal OUT representing the charge state of the ferroelectric memory cell 10. Typically, the reference capacitor 78 is the parasitic capacitance associated with the complementary bit line BL 79 not used in the current reading cycle. The sense amplifier 76 is most often implemented as a cross coupling bistable inverter circuit that invests in one of two states depending on which of the voltages, on its two input lines 70, 79, is the highest. Therefore, it is desirable to set the voltage on the reference capacitor 78 or associated bit line 79 to an intermediate voltage, the complementary voltages are induced in the active bit line 70 by the complementary states of the ferroelectric cell 10. All the The operations described above are controlled, pre-charged and discharged by a logic circuitry 80 having two power supply inputs to ground and the voltage Vcc of the DC power supply. As a result, by blocking the use of circuitry that multiplies the complex voltage, all operations within the memory circuit are limited to a maximum voltage swing of Vcc. However, many designs of ferroelectric memories have been based on the voltage of the power supply Vcc which is 5VDC. As a general rule but loose, for a memory cell of the ferroelectric capacitor, the applied bias voltage Vmax is limited to no more than about half the voltage of the power supply Vcc. The reading of a ferroelectric cell is typically done by dividing the charge stored in the ferroelectric capacitor with a larger capacitance, associated with the bit line. Due to this voltage drop and other voltage losses across several capacitors in the read and write circuitry, it is common for the Vmax or Vsat to be five times the coercive voltage Vc. In any case, low values of coercive voltage Vc are reflected in low values of saturation voltage Vsat. Assuming a voltage of the power supply Vcc of 1.8VDC, it is desired that the coercive voltage Vc be 0.5 to 0.6VDC, yet it is commuted by 0.9VDC. In general, if the coercive voltage Vc is low, the saturation voltage Vsat is also low. Theoretically, it is possible from the point of view of the reduced voltage operating range to simply reduce the thickness of the ferroelectric layer in the ferroelectric cell, since the ferroelectric effects are dependent on the applied electric field, that is, the applied potential divided by the thickness of the ferroelectric layer. Therefore Vc and Vmax would scale downwards with the thickness of the ferroelectric material. However, currently ferroelectric materials are imperfect electrical insulators, and an unacceptably high electrical conductivity will prevent the ferroelectric cell from operating in a real system. The problem is linear, that is, non-ohmic, for example by electronic quantum jump. As a result, a small increase in the local effective electric field could result in a very large increase in electric current. These effects result in the commonly accepted limitation, that the ferroelectric layer has a minimum thickness of 0.23 μm or at least not less than 0.15 μm. At lower thicknesses, the leakage current through the ferroelectric material becomes excessive. As a result of the minimum thickness, the voltage applied across the ferroelectric layer must exceed a minimum value that produces adequate storage of capacitive load. The physical operation of a ferroelectric cell is believed to follow the mechanism illustrated in FIG. 5 for a simple ferroelectric material such as PZT (PbZrTi03), PLZT (PbLaZrTi03), and other well-known materials. These first three materials are best characterized as alloys of the compounds PbZr03, PbTi03, LaZr03, and LaNb03, in the case of PLZT. Similar characterizations should be made for PNZT (PbNbZrTi03). A unitary cell for these materials is usually tetragonal, that is, a rectangular cell that has three perpendicular unitary vectors, one that has a value c and the other two that have the same value a. For most ferroelectric materials, c is greater than a. The c / a relation will define what is the tetragonality factor of the ferroelectric material. The unit cell includes eight rare earth atoms 82 of lead (Pb), lanthanum (La), or Niobium (Nb) at their corners, six oxygen atoms (O) 84 to half of the six rectangular faces, and one atom of cation of titanium (Ti), zirconium (Zr), etc., located generally in the center of the tetragonal cell. However, below the Curie temperature, the position of the low energy cation is located either above or below the center of the cell, in one of the off-center positions 86a, 86b. The displacement of the cation from the center of the cell provides the bistable ferroelectric behavior. One of the two off-center positions 86a, 86b that the cation assumes determines the polarization state of the cell. It is desired to take advantage of the known characteristics, advantages and disadvantages of the ferroelectric memory cells to produce a particularly advantageous cell design for low voltage operation.

BRIEF DESCRIPTION OF THE INVENTION The invention can be summarized as a ferroelectric capacitor cell having a crystallographically oriented ferroelectric layer formed in a metal oxide electrode layer. The ferroelectric material is chosen to have a composition having a low tetragonality factor, that is, a low c / a ratio for a tetragonal perovskite. In particular, the tetragonality factor could indicate a composition of a complex ferroelectric alloy that provides less optimal ferroelectric characteristics. However, a ferroelectric cell is likely to exhibit better fatigue characteristics due to the lower resistance of the lower tetragonality factor, and the best features could not be polarized with voltage levels used in densely integrated memories. The effect has been demonstrated for lead titania lanthanum zirconium (PLZT) and lead titania niobium zirconium (PNZT).

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic representation of a ferroelectric memory cell. FIG. 2 is a cross-sectional view of a ferroelectric memory cell to which the invention can be applied. FIG. 3 is a graph illustrating the important ferroelectric parameters of a ferroelectric cell. FIG. 4 is an electrical schematic diagram illustrating the read / write circuitry associated with a ferroelectric memory cell. FIG. 5 is a schematic orthographic illustration of the crystal structure of ferroelectric materials such as PZT, PLZT and other perovskites.

FIG. 6 is a graph of hysteresis curves for two compositions of lead lanthanum zircotitanate. FIG. 7 is a plot of hysteresis curves for different polarization voltages for a PLZT composition of the invention.

FIG. 8 is a graph of hysteresis curves for three niobium lead zircotitanate compositions. FIG. 9 is a plot of the switched polarization as a function of the bias voltage for PNZT composite cells with three values of niobium content. Fig. 10 is a graph of the coercive voltage as a function of the bias voltage for the three cells of PNZT. FIG. 11 is a bipolar switched polarization graph as a function of fatigue cycles for the three PNZT cells.

DETAILED DESCRIPTION OF THE PREFERRED MODALITY The conclusion partially based on some of the considerations presented in the background section is that, for advanced ferroelectric integrated circuits, the coercive voltage Vc and the maximum operating voltage Vmax should not be more than acceptable high values, contrary to previous art where it is believed that the coercive voltage should be as high as possible. The present invention seeks to take advantage of the opposite effect considerations between large tetragonality which promotes good ferroelectric performance but poor fatigue characteristics and excessively high operating voltage, and small tetragonality exhibiting poor ferroelectric characteristics but good fatigue characteristics and low operating voltages . The c / a factor of the ferroelectric material, illustrated in FIG. 5, has major implications for ferroelectric behavior and fatigue characteristics. A small c / a ratio means that the unit cell is closer to a cubic symmetry, while a larger ratio results in a greater tetragonality of the cell. In general, the greater the c / a ratio, the greater the polarization of the material, which is manifested by large values of the maximum polarization Pmax, and of the remaining polarization Pr. It would seem that a large c / a ratio produces a more hysteresis cycle rectangular 64, thus contributing to a large coercive voltage Vc. However, as explained above, a large coercive voltage Vc may not always be desirable. It also seems that a large c / a ratio contributes to the fatigue characteristics and could reduce the quadrature hysteresis as an additional result. Perovskite materials almost always grow above the Curie temperature, so that the material thus grown has a cubic grid structure with a simple grid dimension of a '. In the crystallographically oriented materials needed for advanced ferroelectric integrated circuits, the cubic material that grew like this is oriented some degrees epitaxially towards the underlying mold layer of, for example, LSCO. As the material cools down below the Curie temperature, the material is converted to the tetragonal structure of FIG. 5. Ignoring the effects of thermal expansion at remote temperatures of the transition, as the material cools through the phase transition, the grid constant decreases in two dimensions from a 'to a, while in the other dimension the grid constant increases from a 'to c. However, the newly tetragonal material remains atomically anchored to the substrate that does not undergo such a transition. As a result, the transition prints a large amount of stress on the ferroelectric material, particularly near the interface with the mold layer, and the stress is greater for larger c / a ratios. Such high levels of stress are expected to lead to various mechanisms that contribute to fatigue and printing on crystallographically oriented ferroelectric materials. It is observed that in polycrystalline ferroelectric materials, typical in the prior art, there is no atomic molding, and the tetragonal crystals can accommodate an inequality of the highest grid in the faces of the crystal. Thus, particularly for tetragonal, crystallographically oriented perovskites, a large c / a ratio implies a large amount of induced stress that could seriously increase fatigue. It is also believed that a large ratio of c / a leads to slower commutation of the ferroelectric polarization. A second effect is that there are three possible orientations for the tetragonal structure as the material cools from the growth temperature to below the Curie temperature. The structure of FIG. 5 is based on the preferred orientation in general, that the axis c is perpendicular to the plane of the mold layer. This is referred to as a domain c. However, on a local scale, it is also possible that one or the other of the two axes a is perpendicular to the mold plate with the axis c falling in the plane. These orientations are domains a. The existence of orientations both a- and c- produce 90 ° domain walls between the two differentially oriented regions. Uniform c domains are preferred, and in general the a domains will be set to the orientation of the neighboring c domains and form larger domains. However, if there is a larger value of c / a, any fixation at a lower temperature includes a significant distortion of the existing crystal structure and the transition, while favorable, is difficult to activate. That is, multiple orientations could be metastable. Song et al. have explained this effect in "Activation field of ferroelectric (Pb, La) (Zr, Ti) 03 capacitors", Appl i ed Physi cs Let t ers, vol. 71, no. 15, October 1977, pp. 2211-2213. In addition, the operation of ferroelectric cells ultimately depends on the switching of polarization domains. It is well known that ferroelectric materials containing multiple domains with 90 ° domain walls between them require higher field to commute, compared to those with only 180 ° domain walls. Therefore, it is desirable to suppress the multiple orientations arising from domains c in the ferroelectric material oriented predominantly on the c-axis. Based on these considerations, it is now believed that ferroelectric integrated circuits that need to be operated at lower voltages should include a lower tetragonality ferroelectric material, that is, a reduced c / a ratio although one has a value above the unit. The c / a relationship could be described as a tetragonality factor for materials that have the same or almost the same grid vectors on the a axis in two directions. Although the polarization effects could be impaired by a lower c / a ratio, they could still be very suitable. At the same time, the fatigue characteristics are improved due to the reduced effort. In addition, it is believed that the material is easier to fix in a material oriented merely on the c-axis. In addition, ferroelectric cells of lower tetragonality are expected to commute more easily. That is, the switching speed is increased. It is believed, based on the experiments presented below, that a c / a ratio of about 1.01 is most preferred, and beneficial results are obtained with values of the tetragonality factor that extend down to 1.005. A favorite class of ferroelectric material is PLZT, ie Pbj ^ La ^ r and ij.y. A more compact designation is, for example, 7/65/35 where x = 7%, y = 65%, and l-y = 35%. The designation thus amounts to x / y / l-y. In general, a large value of x decreases the ferroelectric effects but favors the crystalline quality due to the diminished tetragonality. PLZT with high values of x of about 65% are used for electro-optical devices, but at these values of x, the material is not tetragonal. It is believed that for reduced voltage operation, PLZT should have a La x content of between 6 and 12%. One of the examples presented by Ramesh in U.S. Pat. 5,270,298 includes a ferroelectric cell structure with PLZT having a composition of x = 10%, y = 20%, ie 10/20/80. Note that the cited application uses different definitions for x and y. Two prototype capacitor structures were manufactured according to the method of the cited patent. One composition was (0/20/80) and the other was (10/20/80), the x is equal to 0% and 10% alternately. The crystallographic parameters for thin films of these materials are given in TABLE 1. Yang et al. report similar results in "Low voltage performance of Pb (Zr, Ti) 03 capacitors through donor doping", Applied Physi cs Let t ers, vol. 71, no. 25, December 1997, pp. 3578-3580. x (%) c (nm) to (nm) c / a OR 0.411 0.395 1.034 3 0.410 0.396 1.030 10 0.4052 0.396 1.016 TABLE 1 Hysteresis curves were measured for the two samples. The results are shown in FIG. 6. The PZT sample (x = 0) in cycle 90 shows a very square characteristic, while the PLZT sample with x = 10% in cycle 92 shows a less square behavior. The last measurements of the hysteresis curve for PLZT capacitors x = 0.3 show intermediate results of the graphs of FIG. 6. The PLZT sample x = 0.1 was tested for a number of pulsed polarization voltages. The hysteresis cycles are shown in FIG. 7: cycle 94 for polarization of 5 V; 96 cycle for 2.3V polarization; and cycle 98 for 2V polarization. For the PLZT sample x = 0.1, the saturation polarization is about 35 μC / cm2 at 5V, and the coercive voltages Vc are all about 0.6V. The PLZT capacitors x = 0.1 were tested for fatigue and both at room temperature and at 100 ° C.

Both the fatigue and test impulses were 2V. The samples showed essentially no fatigue at 1011 cycles. Other tests with PLZT capacitors x = 0.03 showed better initial polarization susceptibility, but fatigue above 109 cycles resulted in deterioration of the polarization susceptibility below PLZT x = 0.1. As previously suggested, it is believed that higher lanthanum ferroelectric materials will switch at lower energies than ferroelectric materials with less highly polarized lanthanum, due to the smaller presence of a-axis domains. in an operational cell, this benefit is believed to extend to switch with shorter pulse widths, an effect becomes important with ferroelectric memories that should switch to substantially less than 1 μm when incorporated into computer systems, for example, using impulse widths of 100 ns. The experimental results are not available for a direct comparison between cells similarly manufactured with ferroelectric materials of different tetragonality. However, pulse width measurements show that the PLZT capacitors could have somewhat less polarization switchable at larger pulse widths than the PZT capacitors, presumably because PLZT has a lower tetragonal factor than that of PZT. However, as the pulse width decreases towards 100 ns, the switchable polarization of PZT drops substantially while PLZT undergoes a smaller decrease. In this way, it is expected that the PLZT with higher lanthanum will operate better with very expensive pulse widths. These results for PLZT show that the superior results are obtained with a factor of tetragonality c / a of 1.016 more than 1.030. It is believed that a tetragonality factor of 1.01 should provide even better results for low voltage operation of the ferroelectric cell, and a tetragonality factor of 1,005 would be beneficial. Another ferroelectric material of great interest is PNZT, ie Pb ^ Nbj-ZryTij.yOj. It is observed that this material behaves similarly to PLZT, although less dramatically in the effects of polarization, but the effects of fatigue and synchronization are substantial. A series of prototype test capacitor structures were manufactured using the now conventional technique of pulsed ablation deposition (PLD).

A oriented silicon substrate (100) was first covered with a TiN barrier layer. The substrate covered with TiN was then covered in a PLD process with a platinum contact layer. The ferroelectric layers were then grown by means of PLD in an oxygen environment at 600 ° C. The ferroelectric cell consisted of a lower contact / mold layer of LSCO, a ferroelectric layer of PNZT, and an upper contact layer of LSCO. The crystallographic parameters for thin films of Pbi_xNbxZro.2Tio.8O3, ie PNZT (x / 80/20), are given in TABLE 2.

X (%) c (nm) to (nm) c / a 0 0.4103 0.3968 1.034 6 0.4088 0.3975 1.0284 10 0.4083 0.3991 1.0233 TABLE 2 The hysteresis curves for capacitor structures for the three compositions were measured with a polarization voltage of 4.5V, as shown in FIG. 8. Cycle 100 shows the hysteresis curve for x = 0, ie PZT; cycle 102, for x = 6%; and cycle 104, for x = 10%. The polarization properties decreased somewhat for x = 6% and substantially more for x = 10%. However, the sample rich in niobium exhibits good hysteresis characteristics. Similar hysteresis characteristics were obtained using a barrier layer of (Ti0 9Al0 1) N with a variant content of niobium. Close analysis of these curves shows interesting results as the maximum applied voltages are reduced and as the devices become fatigued. In FIG. 9 curves for the switched polarization are shown P = P * -P "as a function of the applied maximum voltage Vmax The curve 110 gives the switched polarization for an Nb content of x = 0%, the curve 112 for x = 6%, and curve 114 for x = 10% The sample without Nb, that is, from PZT, exhibits the largest commuted polarization at the highest switching voltage of 5 V. The sample with x = 6% is somewhat reduced , and the highest niobium content exhibits the lowest commuted polarization.At 4V, the difference is even larger, however, as the maximum voltage is reduced below 3V, the situation changes.At 2V, the results are the same that for 6% and 10%, the coercive voltages Vc are shown as a function of the applied maximum voltage Vmax for the three equal values of Nb content in Figure 10. Curve 120 gives the value for x = 0; 122, for x = 6%, and curve 124, for x = 10% The low values of Vc correspond to low values of Vsat and better properties of low voltage. Fatigue results are even more interesting. The memory cells are fatigued with bipolar pulses of ± 3V at 1 MHz. Their bipolar switched polarizations ± P were measured at various times during the fatigue cycle, and the results are shown in FIG. 11. Curve 130 gives the switched polarizations for x = 0; the curve 132, for x = 6%; and curve 134, for x = 10%. Without fatigue, the cells with the lowest Nb content showed some better switched polarization than the cell with x = 10%. However, after the fatigue was extended, cells with x = 0 began to suffer severe deterioration, and those with Nb content of 6% and higher showed better overall results. In this way, it is seen that the content of La and Nb should increase to levels above those normally recommended for commercially viable ferroelectric memory cells. For PLZT, the x fraction of lanthanum should be at least 3% and preferably more than 6% up to 12%, when the Zr fraction is approximately 20%. It is believed that 15% is the fraction of the preferred maximum if reasonable polarizations are to be achieved. The highest value of La content is limited by the formation of PLZT in a non-ferroelectric phase. The fraction of Zr can be increased to 50%, for which the fraction of La is much smaller, preferably around 2%. For PNZT, it is believed that the same numbers apply to fractions of Zr and Nb. Expressed in terms of the c / a factor of tetragonality, for PNZT it should be reduced below 1.029 and preferably below 1.025. Beneficial results are expected with the tetragonality factor of PNZT having a value in a range extending below 1.020. The memory cell presented in FIG. 1 is represented only to explain the exact structure used in the examples. Other structures of crystalline-oriented materials could be used. Particularly preferred are those that do not require any platinum, such as that which incorporates an intermetallic barrier, described by Dhote et al. in U.S. Patent Application. 08 / 582,545, filed January 3, 1996, now U.S. Pat. No. 5,777,365, and by Dhote et al. in U.S. Patent Application. 08 / 871,059, filed June 19, 1997. The first corresponds to PCT Publication WO 97/25745.

Although the invention has been described with respect to particular compositions of PLZT and PNZT, it is not limited thereto. Rare earth elements other than lanthanum and niobium could be used in fractions that reduce tetragonality with respect to a fraction that produces higher polarization effects. The invention thus provides a ferroelectric cell that eliminates unnecessary polarization to reduce the effort required, resulting in less fatigue and higher switching speeds.

It is noted that in relation to this date, the best method known by the applicant to carry out the aforementioned invention, is the conventional one for the manufacture of the objects to which it relates.

Claims

CLAIMS Having described the invention as above, the content of the following claims is claimed as property:

1. A ferroelectric memory cell, comprising: a first metal oxide electrode; a ferroelectric layer formed on the first electrode, having a perovskite crystal structure, and comprising Pb, Nb, Zr, Ti, O; a second electrode formed in the ferroelectric layer; and circuitry connected to the two electrodes for supplying power, controlling and reading a charge stored in the ferroelectric layer and having a maximum DC power supply voltage of no more than 3V, characterized in that the ferroelectric layer comprises a sufficient fraction of Nb for allow the operation of the circuitry at the maximum DC power supply voltage.

2. The memory cell of claim 1, characterized in that the x fraction of Nb, compared to a 1-x fraction of Pb, is at least 10%.

3. A ferroelectric cell, characterized in that it comprises a first electrode containing a metal oxide, a ferroelectric layer formed on the first electrode, having a perovskite crystal structure, and containing Pb1_xNbxZryTi1_y03, where x is equal to or greater than 10%; and a second electrode formed on the ferroelectric layer.

4. The memory cell of claim 3, characterized in that y is between 15% and 30%.

5. The memory cell of claim 4, characterized in that y is approximately 20%.

6. The memory cell of claim 3, characterized in that x is not greater than 15%.

7. A ferroelectric cell, comprising: a first electrode containing a metal oxide; a ferroelectric layer formed on the first electrode and containing a first quantity of a first rare earth element, a second quantity of a second rare earth element, at least one cation element, and oxygen, and forming a first crystal structure of perovskite with a first factor of tetragonality; and a second electrode formed in the ferroelectric layer; characterized in that the first and second quantities are chosen to have values such that the first tetragonality factor is less than a second tetragonality factor, and a first polarization characteristic of the first perovskite crystal structure is less than a second characteristic. of polarization, the second tetragonality factor and the second polarization characteristic occur if the ferroelectric layer were formed in a second perovskite crystal structure with nothing of the first rare earth element. The ferroelectric cell of claim 7, characterized in that the first and second quantities are chosen to have values such that the first tetragonality factor is less than a third tetragonality factor, and the first polarization characteristic is less than a third polarization characteristic, the third tetragonality factor and the third polarization characteristic are produced if the ferroelectric layer were formed in a third perovskite crystal structure with nothing of the second rare earth element. The ferroelectric cell of claim 7, characterized in that it further comprises circuitry connected to the two electrodes for supplying power, controlling, and reading a charge stored in the ferroelectric layer and having a maximum DC power supply voltage of no more than 3 V. 10. The ferroelectric cell of claim 7, characterized in that the ferroelectric layer contains Pb, La, Zr, Ti and O. 11. The ferroelectric cell of claim 7, characterized in that the ferroelectric layer contains Pb, Nb, Zr, Ti and O.