KR20010075336A - Ferroelectric thin films of reduced tetragonality - Google Patents

Abstract

As integrated into the ferroelectric material, in particular the crystallographically oriented stacked ferroelectric cell, Pb _1-x La _x Zr _y Ti _1-y O ₃ or Pb _1-x Nb _x Zr _y Ti _1-y O ₃ is suitably a large number of La or Having Nb content, the unit cell becomes a nearly cubic rectangle, reducing the stress effect. More preferred c / a constant value is about 1.01. Exemplary synthetic ranges of x are La at 6 to 20% and Nb at 3 to 15% when y is 20%. The reduced polarization voltage is consistent with integrated ferroelectric memory operating below 3.0V.

Description

Ferroelectric thin film with reduced tetragonality {FERROELECTRIC THIN FILMS OF REDUCED TETRAGONALITY}

Ferroelectric RAMs (FRAMs) do not require energy to maintain their electrically applied polarization state, so the ferroelectric RAMs offer the potential as non-volatile memory to replace silicon memory. The schematic general structure of the ferroelectric ram 10 includes two capacitor 12, 14 plates with a body 16 interposed therebetween, as shown in FIG. 1. The ferroelectric material 16 not only has an insulator constant that substantially exceeds the unit source, but the ferroelectric has appropriate conditions of bistable. The capacitor plates 12, 14 support the ferroelectric in an upward or downward polarization state, and the ferroelectric body 16 remains in this state even after the polling voltage is removed. This is generally that no charge (or voltage) remains above the cell 10 without any applied power applied. Sometimes, the charge can be measured later. Thus, the ferroelectric RAM 10 is a nonvolatile memory.

Conventionally, the ferroelectric ram 10 is sandwiched between two metal electrodes having a capacitor structure. The ferroelectric ram 10 includes a crystalline ferroelectric material. However, this design is less reliable and aging problems arise.

More recently, Ramesh and colleagues have developed crystallographically oriented ferroelectric cells using metal oxide electrodes. Dote et al. Disclose a lower electrode based on platinum in US patent application Ser. No. 08 / 578,499, filed Dec. 26, 1995, and also PCT Publication No. 97/23886, filed Jul. 3, 1997. have.

A cross section of an exemplary structure of dots or the like for a ferroelectric ram 20 similar to a silicon dynamic ram is shown in FIG. 2. The ferroelectric ram structure must be duplicated several times to form a large amount of ferroelectric ram integrated circuits, and other support circuitry needs to be formed on the same chip. The entire ferroelectric ram structure is known from Lamarsh, in the already cited US patent applications and applications, with a few exceptions. Kinney provides a good overview of ferroelectric integrated circuits in "Signal magnitudes in high density ferroelectric memories" Intergrated Ferroelectrics, vol. 4, 1994, pages 131-144. The ferroelectric ram 20 is formed on the (001) -directional crystalline silicon substrate 22, so that other silicon circuit elements can be easily incorporated. Metal-oxide-semiconductor (MOS) transistors diffuse dopants of a conductive type opposite to the substrate 22 in source and drain wells 24 and 26. formed by diffusing or implanting. The intervening gate region is covered over a gate structure 28 that includes a lower oxide gate and an upper metal gate line, for example aluminum, to control the gate.

A first inner-level insulating layer 30, for example silicon second oxide, is applied over the substrate 22 and the transistor structure. A contact hole 32 passes through the first inner-level insulating layer 30 over the source well 24, is photolithographically etched, and into the transistor source 24. To form a polysilicon contact plug, polysilicon is filled therein. A metal source line 34 is photolithographically outlined on top of the first inner-level insulating layer 30 and is in electrical contact with the polysilicon plug 32.

A second inner-level insulating layer 36 is then applied over the first inner-level insulating layer 30. The other contact hole 38 etches through the first and second inner-level insulating layers 30 and 36, over the drain well 26. And polysilicon is filled in contact with the transistor drain 26. The process is very standard in silicon technology.

Then, although commercial manufacturing masked dry plasma etching is generally performed, the lift-off mask has a larger area of holes above the drain contact hole 38 for the desired size of the capacitor. Attached and defined. On the mask and in the hole are applied in a series of layers. Polysilicon layer 40 provides good electrical contact to the polysilicon plug 38. TiN layer 42 and platinum layer 44 form a conductive barrier layer between the polysilicon and the oxidized metal-oxidized contact. Polysilicon has semiconducting properties, but if its surface is oxidized to SiO ₂ , a stably insulated layer is formed to prevent electrical contact. Although other metal oxides may be used, in particular the formation of gray titaniumite as a layer, a conductive metal oxide layer 46, preferably lanthanum strontium cobalt oxide (LSCO), over the platinum layer 44 Apply the same ash titanite layer. Although the approximate composition of La _1-X Sr _X CoO ₃ is possible at 0.15 ≧ _x ≧ 0.85, the material has a composition nominally given by La _0.5 Sr _0.5 CoO ₃ . LSCO forms an acceptable electrical contact and further promotes directional growth of the gray titanium ferroelectric material.

The photomask is removed leaving the lower loading layers 40, 42, 44, 46 shown in FIG. 2. Another photomask is defined to allow conformal application of the Z-shaped field-oxidation layer 48. The Z-shaped field-oxidation layer 48 covers the sides of the predefined lower loading layer, has an edge that enlarges the edge of the upper surface of the lower loading layer, and extends outward from the bottom of the lower loading layer. It has an extended foot, but leaves a central hole for later application on top of the ferroelectric load. The field-oxide layer 48 electrically insulates the ferroelectric applied later from the side portion of the lower electrode.

In the past, the field-oxide layer 48 was formed of SiO ₂ or TiO ₂ . However, none of these materials are ideal. The ash titanium ferroelectric tends to form in a mixture of ash and pyrochlor phases that are etched differently as a result of unreliable etching when applied over these materials. A better material for the field oxide layer 48 is bismuth titanate (close stoichiometric composite Bi ₄ Ti ₃ O ₁₂ ), which is ash titanium and grown by the same growth process along the other ash titanium layer. Can be done. Lamarsh, in US Patent Application No. 5,248,564, discloses that Bi ₄ Ti ₃ O ₁₂ is a strong template layer to promote the growth of crystallographically scented gray titanium stones on non-oriented substrates. Thus, the Bi ₄ Ti ₃ O ₁₂ field oxide layer 48 is assured that a good ferroelectric is grown thereon. Other gray titanium materials may be used as a substitute for the bismuth titanate as long as they exhibit a low dielectric constant without high conductivity and, for example, no ferroelectricity. For a more effective template, the gray titaniumite forming Bi ₄ Ti ₃ O ₁₂ has a layered structure, ie a c-axis lattice up to twice the a and b axes.

After the formation of the field oxide layer 48, another photomask of the field oxide layer 48 including holes around the bottom stacks 40, 42, 44, 46 is applied and defined, but the outer periphery of the bottom is covered by the field. Overlying the feet 59 of the oxide layer 48. The ferroelectric layer 50 is then applied under conditions that are crystallographically suitable for directional growth. Preferably, the ferroelectric layer 50 is lead lanthanum zirconium titanate (PLZT) or lead lanthanum zirconium titanate (PNZT). Application of the succinate ferroelectric layer on LSCO or other similar sitrite conductive electrodes admits that the ferroelectricity can be applied at relatively low temperatures, but still specifies suitable crystals. An upper conductive oxide-metal layer 52 is applied over the ferroelectric layer 50, and preferably the upper conductive metal-oxide layer 44 of gray titanium, such as LSCO, is symmetrically formed. An upper platinum layer 54 is applied over the upper conductive metal oxide layer 52. The layer 54 is not believed to include critical technology, and its platinum composite has been chosen only as a temporary solution. The composite will be changed to TiW or other metals common in silicon technology. After the upper platinum layer 54 is applied, the photomask is removed leaving the top deployment structure shown in FIG.

A third inner-level insulating layer 56 is applied and etched to cover the ferroelectric loading. The layer 56 is more intended as a passivation layer than with inner-level insulation.

The upper electrode 54 etches the passage 60 through a third inner-level insulating layer 56 overlying the ferroelectric layer, fills the passage 60 with Ti / W, and the Ti / W plug. It is in electrical contact by delineating a metal capacitor line 62 of aluminum in electrical contact with it.

Dhote et al. Described the application of the lower platinum layer 44 at a relatively high temperature around 500-550 ° C. to the ferroelectric load (the ferroelectric layer and the metal-oxide sandwiched between the two at a higher thermal budget). Acknowledgment of the application of the layers) is defined as the integration of temperature (measured in degrees C.) and the time of the sample at that temperature. Since the three layers, the PNZT layer 50, the upper LSCO electrode 52, and the upper platinum layer 54 are generally applied in a single chamber at a single temperature, the thermal budget Product of application temperature and total application time.

PNZT is a well known ferroelectric medium. Dhote et al. Present particular examples of PNZT composites as Pb _0.04 Nb _0.18 Zr _0.78 TiO ₃ and Pb _0.04 Nb _0.28 Zr _0.68 TiO ₃ . In other words, PNZT lacks lead on the one hand and rich in lead and zirconium on the other.

The problem that arises with some types of ferroelectric memory is their fatigue failure. The ferroelectric or polarization properties of ferroelectric cells change many read-write cycles. While polycrystalline cells are extremely bad from fatigue failure, the crystallographically oriented cells slow down their greater resistance to fatigue failure. Nevertheless, it is still believed that fatigue failure is a problem for crystallographic directional cells.

In ferroelectric cells, it is necessary to understand the polarization characteristics of ferroelectric cells in order to quantify fatigue failure and other operating characteristics. Ferroelectric hysteresis loop 64 is shown in FIG. 3. The horizontal axis represents the voltage across the cell. The vertical axis represents the polarization of the material, whether instantaneously applied or residual (residual magnetic), ie without voltage applied. The polarization is proportionally related to the time integration of the flowing charge or the shape of the cell. The hysteresis curve is highly nonlinear. These properties are assumed to be symmetric, although not in fact true.

The hysteresis curve shown approaches the maximum polarization value Psat as the applied voltage approaches a saturation voltage (Vsat). However, the polling is generally formed along the voltage direction with Vmax yielding Pmax which is about 90% of Psat. The difference in polarization between polls of ± Vmax is indicated by P *, ie P * = 2Pmax, in the symmetric hysteresis curve. If the cell is pulsed with Vmax followed by polarization Pmax, but then the voltage is reduced to V = 0, the polarization nevertheless remains as residual polarization Pr. If the cell is negatively polled, the polarization leaves a negative residual polarization with a symmetric hysteresis curve equivalent -Pr. Assuming that the read is formed by positive polling with the applied voltage Vmax, the measured charge on the polling corresponds to either unswitched polarized light P or switched polarized light P *. The readout circuitry must distinguish the difference in the pulsed polarization ΔP = P * -P ^. For a symmetric hysteresis curve the pulsed polarization ΔP is equal to 2Pr.

In general, in many implementations, the hysteresis curve should be as rectangular as possible. The high voltage Vc should be the maximum of a given Vmax. This is based on the fact that the magnetic polarization Pr should be made as large as possible and that the residual polarization should increase with the high voltage. However, there are some tradeoffs.

Another condition is that if ferroelectric memories are to be commercialized, they must be compatible with other silicon integrated circuits used in, for example, personal computers, computer workstations, and other computer control applications. For many years, digital silicon integrated circuits, whether logic or memory, have been powered by a 5 VDC DC voltage Vcc. However, recently improved integrated circuits have been designed to be powered by lower voltages, for example 3.0 VDC, 2.3 VDC, and 1.8 VDC. Reduced voltages reduce both the problems associated with thermal consumption in extreme density integrated circuits and the increase in battery capacity of portable computers.

An example of the critical readout circuitry associated with the ferroelectric cell 10 is shown in the circuit block diagram of FIG. This embodiment follows the specification by Kinney et al. Each ferroelectric cell 10 is associated with a read transistor 66 and corresponds to the MOS transistor of FIG. 2. The word line 68 controls the read transistor 66 located in the column of memory cells 10 except for a direction perpendicular to the word line 68. The read transistor 66 selectively connects the ferroelectric cell 10 to the bit line 70, which is connected in the form of a row of memory cells 10. The word line 68 and bit line 70 act vertically on a rectangular array of memory cells 10. Due to the hysteresis effect in the ferroelectric medium, it is important to provide selective biasing of the other electrode of the ferroelectric cell 10 through the plate line 72 parallel to the word line 68 during the readout process. .

During the readout process, the ferroelectric cell 10 is temporarily connected to the bit line 70 and the charge stored above the cell 10. The larger parasitic capacitor 74 associated with the bitline 70, whether positive or negative, is shared. The sense amplifier 76 compares the voltage with a reference voltage and inputs it to the sense amplifier 76 of line 79. The sense amplifier 76 outputs a digital signal OUT indicating the state of charge of the ferroelectric memory cell 10.

Typically, the reference capacitor 78 is a parasitic capacitance associated with the complementary bit line-BL 79 that is not used in the current read cycle. The sense amplifier 76 is most often a cross-coupled bistable latch circuit latched to one of two states depending on which of the voltages on its two input lines 70, 79 is the highest. Is implemented. Accordingly, the voltage on the reference capacitor 78 or associated with the bit line 79 may be converted into the complementary voltages induced on the active bit line 70 by the complementary states of the long light source cell 10. It is desirable to set the voltage to be mediated. All of the operations described above are controlled, pre-charged and discharged by logic circuit 80 having two power supply inputs at ground and the DC power supply voltage V _cc . As a result, all operations in the memory circuit except for the complex voltage multiplex multiplication circuit circuit are limited to the maximum voltage swing of V _cc .

However, most designs for long light source memories have been based on the power supply voltage V _cc which is 5 VDC. As a general but loose rule, for long light source capacitor memory cells, the applied polling voltage V _max is only limited to approximately one half of the power supply voltage V _cc . Reading of the long light source cell is typically accomplished by dividing the charge stored on the long light source by the larger capacitance associated with the bit line. Due to this voltage drop and other voltage losses in the various capacitors in the read and write circuit, V _max or V _sat is five times the constant voltage V _c . In any case, lower values of the constant voltage V _c are reflected in the saturation voltage V _sat . Assuming the power supply voltage V _cc is 1.8 VDC, it is desirable to make the constant voltage V _c between 0.5 and 0.6 VDC so that it is all switched at 0.9 VDC. In general, if the constant voltage V _c is low, the saturation voltage V _{sat is} also low.

Theoretically, in terms of reduced voltage drive range, the ferroelectric effects depend on the applied electric field divided by the applied potential divided by the thickness of the ferroelectric layer, thus reducing the thickness of the ferroelectric layer in the ferroelectric cell. It is possible. Thus, V _max or V _sat will be reduced by the thickness of the ferroelectric. However, current ferroelectric materials are incomplete electrical insulators, and unacceptably high conductivity will render the ferroelectric cell inoperable in an actual system. The problem is linear, for example by electronic quantum hopping, i.e. not ohmic. As a result, small increases in the local effective electric field can result in very high increases in current. These effects result in a commonly accepted limitation that the ferroelectric layer has a minimum thickness of at least 0.23 μm or at least 0.15 μm. At laser thicknesses, the leakage current across the ferroelectric is excessive. As a result of the minimum thickness, the voltage applied to the ferroelectric layer must exceed the minimum value that results in proper capacitive charge storage.

The physical operation of ferroelectric cells is believed to follow the mechanism shown in FIG. 5 for simple ferroelectric materials such as PZT (PbZrTiO ₃ ), PLZT (PbLaZrTiO ₃ ), and other well known materials. These first three materials show the best properties as alloys of PbZrO ₃ , PbTiO ₃ , LaZrO ₃ , and LaNbO ₃ compositions in the case of PLZT. Similar properties should be present for PNZT (PbNbZrTiO ₃ ). The unit cell for these materials is generally a tetragonal system, ie a rectangular cell with three vertical unit vectors, one of which has the value c and the other two having the same value a. For most ferroelectric materials, c is greater than a. The c / a ratio will be defined as the tetragonal factor of the ferroelectric material. The unit cell comprises eight rare earth elements 82 in lanthanum (La) or niobium (Nb) at its corners of lead (Pb), and six oxygen (O) elements (84) in its six rectangular planes. And generally a cation element such as titanium (Ti), zirconium (Zr), or the like located at the center of the tetragonal cell. However, below the Curie temperature, the low energy cation position is located one of the top and bottom of the cell center at one of the offset positions 86a, 86b. The displacement of the cation from the cell provides bistable ferroelectric properties. Any one of the two offset positions 86a, 86b that the cation takes determines the polarization state of the cell.

It is desirable to use known characteristics, strengths, and weaknesses of ferroelectric memory cells to provide a design of a cell that is particularly beneficial for low voltage operation.

The present invention relates generally to ash titanium material. In particular, the present invention relates to ferroelectric materials used in ferroelectric memory cells.

1 is a representative schematic diagram of a ferroelectric memory cell.

2 is a cross-sectional view of a ferroelectric memory cell that can be implemented in the present invention.

FIG. 3 is a graph depicting important phase dielectric parameters of ferroelectric cells.

4 is an electrical schematic block diagram illustrating read / write circuitry associated with ferroelectric memory cells.

FIG. 5 shows a schematic square of the crystal structure of ferroelectric materials, such as PZT, PLZT, and other grayitite.

6 is a graph of hysteresis curves for two compounds of lead lanthanum zitotitanate.

7 is a graph of hysteresis curves for different polling voltages for the PLZT composite of the present invention.

8 is a graph of hysteresis curves for three compounds of lead niobium zitotitanate.

9 is a graph of polarized light switched as a donation of polling voltage for cells composed of PNZT with three values of niobium content.

10 is a graph of high voltage as a function of polling voltage of three PNZT cells.

11 is a graph of bipolar switched polarization as a function of fatigue break cycle for three PNZT cells.

According to one embodiment, the present invention can be summarized as a ferroelectric capacitor cell having a ferroelectric layer directed to crystallization formed on a metal-oxide electrode layer. The ferroelectric material is selected to have a composition having a low tetragonal factor, ie a low c / a ratio for tetragonal perovskite. In particular, the tetragonal factor points to compositions of composite ferroelectric alloys that provide properties inferior to optimal dielectric properties. Nevertheless, ferroelectric cells may exhibit better fatigue characteristics due to lower tetragonal factor, and better characteristics may not be polled by the voltage levels used in integrated memories. The effect was demonstrated for lead lanthanum zirconium titanate (PLZT) and lead niobium zirconium titanate (PNZT).

For improved ferroelectric integrated circuits, the high voltage Vc and the maximum operating voltage Vmax should be only high value available, in contrast to the prior art which believed that the high voltage should be as high as possible.

The present invention benefits from offsetting the conditions between large tetragonality that promotes good ferroelectric behavior excluding poor fatigue failure characteristics and excessive high operating voltages, and small tetragonality that exhibits poor ferroelectric characteristics except good fatigue fracture characteristics and low operating voltages. Try.

The c / a element of the ferroelectric material shown in FIG. 5 has an important relationship to the ferroelectric action and fatigue failure characteristics. A small c / a ratio means that the unit cell is close to cubic symmetry, while a larger ratio is the result of greater tetragonality of the cell. In general, the greater the c / a ratio, the greater the polarization of the material and the polarization of the remaining polarization Pr as evidenced by the large values of the maximum polarization Pmax. The large c / a ratio also results in a more rectangular hysteresis loop 70, which also contributes to the large high voltage Vc. However, as explained before, a large high voltage Vc is not always desirable.

Large c / a ratios contribute to fatigue fracture properties, indicating that the squareness of the hysteresis can be further reduced. These gray titanium materials are almost always grown above the Curie temperature, so that the grown material has a square lattice structure with a single lattice dimension a '. In the crystallographically directional materials required for improved ferroelectric integrated circuits, the grown square material is in several layers, for example LSCO, stacked in direction. As the material cools below the Curie temperature, the material converts to the tetragonal structure of FIG. As the material crosses over a phase transition and neglects the effect of thermal expansion at temperatures far from the transition, the lattice constant is changed from a 'to c in other dimensions. While increasing, decreases from a 'to a in both dimensions. Nevertheless, the new tetragonal material remains extremely close to the substrate that did not make such a transition. As a result, transitions apply a large amount of stress in the ferroelectric material, in particular, the closer to the interface with the template layer, the greater the amount of stress, and the stress is more to obtain a c / a ratio. Big. Such high levels of stress are expected to drive several mechanisms that crystallographically contribute to fatigue fracture and depression in directional ferroelectrics. In conventional polycrystalline ferroelectrics in the prior art, there is no template of atoms, and the tetragonal monocrystalline can accommodate an inadequate pair of higher lattice on the monocrystalline face. Thus, especially for crystallographically oriented tetragonal gray titanite, a large c / a ratio includes a greater amount of stress caused which can seriously increase fatigue failure. It is also believed that a large c / a ratio leads to slower switching of the ferroelectric polarization.

The second effect is that as the material cools from the growth temperature to below the Curie temperature, there are three possible orientations for the tetragonal structure. The structure of FIG. 5 is generally the preferred direction in which the c-axis is perpendicular to the plane of the template layer. This is area c. However, on a local scale, it is also possible that one or the other of the two a axes is perpendicular to the c axis and the template layer lying in the plane. These orientations are a regions. The presence of a and c orientations results in region walls between two different directional regions. Constant c regions are preferred, and generally a regions will anneal the orientation of neighboring c regions and form larger regions. However, if the value of c / a is large, it involves significant distortion from the crystal structure where any annealing at lower temperatures exists, and the transition is difficult to activate even if smooth. The multiple orientations may be metastable. Song et al., "Activation field of ferroelectric (Pb, La) (Zr, Ti) O ₃ capacitors" Applied Physics Letters, vol. 71, no. 15, October 1997, pp. 2221- The effect is described in 2213 ".

In addition, the operation of the ferroelectric cell eventually depends on the switching of the polarization region. It is well known that ferroelectrics containing multiple zones with 90 ° zone walls between them require a higher field to switch as compared to those with only 180 ° zone walls. Here, in the ferroelectric material oriented predominantly in the c-axis, it is preferable to suppress the occurrence of the plurality of alignments from the c region.

Based on the above considerations, ferroelectric integrated circuits that need to be operated at lower voltages should include lower tetragonal ferroelectric materials. That is, the c / a ratio should be reduced even though the value is greater than the unity. The c / a ratio can be described as a tetragonal element for materials with the same or nearly identical a-axis lattice vectors in two directions. Although the orientation effect can be dropped by lower c / a ratios, they are still really suitable. At the same time, the fatigue failure properties are improved due to the reduced strain. In addition, the material became easier to anneal purely to c-axis oriented material. In addition, lower tetragonal ferroelectric cells are expected to switch more easily. That is, the switching speed is increased.

Based on the experiments below, a c / a ratio of about 0.01 is most preferred, and influential results are obtained with the values of the tetragonal element extending until 1.005.

A preferred classification of ferroelectric material is PLZT, ie Pb _1-x La _x Zr _y Ti _1-y . A more complete designation is, for example, 7/36/35, ie x = 7%, y = 65%, and 1-y = 35%. Therefore, the specified amount is x / y / 1-y. In general, a large value of x reduces the ferroelectric effect, but the quality of the crystal is given because of the reduced tetragonality. PLZT, where x is about 65% expensive, is used in optoelectronic devices, but at the x values the material is non-square. For reduced voltage operation the PLZT should have La containing between 6 and 12% x.

One embodiment of the present invention by Lamarsh in US Pat. No. 5,270,298 includes a ferroelectric cell structure with PLZT having a composition of x = 10%, y = 20%, ie 10/20/80. Two basic capacitor structures are constructed according to the method of the cited patent. One composition is (0/20/80), the other is (10/20/80), where x crosses 0% and 10%. In Table 1 the crystallographic parameters for thin films of these materials are given. Yang et al. Reported similar results in "Low voltage performance of Pb (Zr, Ti) O capacitors through donor doping" Applied Physics Letters, vol. 71, no.25, December 1997, pages 3578-3580.

x (%) c (nm) a (nm) c / a 0 0.411 0.395 1.034 3 0.410 0.396 1.030 10 0.4025 0.396 1.016

Pulsed hysteresis curves measure two samples. The results are shown in FIG. The PZT sample (x = 0) in loop 90 is very square in nature, while the PLZT sample with x = 10% in loop 92 is less square in shape. Later, measuring the hysteresis curve for a PLZT capacitor with x = 0.3 shows a result located in the middle of the graphs of FIG.

PLZT samples with x = 0.1 were tested for many pulsed poling voltages. The hysteresis loops are shown in FIG. Loop 94 for 5V polling; Loop 96 for 2.3V polling; And Loop 98 for 2 V polling. For PLZT samples with x = 0.1, the saturation polarization is about 35 μC / cm 2 at 5 V and the high-voltage voltage Vc is all about 0.6 V.

The PLZT capacitor with x = 0.1 is tested for fatigue failure at both room temperature and 100 ° C. The fatigue breakdown and test pulses were both about 2V. The samples showed essentially no fatigue failure up to 10 ¹¹ cycles. Other tests with PLZT capacitors with x = 0.3 show better initial polarization, but fatigue breaks over 10 ⁹ cycles reduce the polarization below that for PLZT with x = 0.1.

As previously suggested, due to less generation of the a-axis region, higher-lanthanum ferroelectrics will switch with lower energy than higher polarized lower-lanthanum ferroelectrics. In operating cells, the advantages are ...

Experimental results are not directly comparable between similarly fabricated cells with different tetragonal ferroelectrics. However, pulse-width measurements may have less polarization that PLZT capacitors can switch somewhat at longer pulse widths than PZT capacitors, since PLZT has lower tetragonal elements than PZT capacitors. However, as the pulse width is reduced towards 100 ns, the switchable polarization of PZT is substantially reduced while PLZT is less reduced. Thus, it is expected that higher-lanthanum PLZTs will work better with very short pulse widths.

The results for PLZT indicate that superior results can be obtained at 1.016 where the square element c / a value is less than 1.030. A square element value of 1.01 should provide better results for low voltage operation of the ferroelectric cell, and a square element value of 1.005 would be beneficial.

Another preferred ferroelectric material is PNZT, Pb _1-x Nb _x Zr _y Ti _1-y O ₃ . Although less dramatic in polarization effects, the material reacts similarly to PLZT. However, the fatigue failure and time effects are substantial.

Series of basic test capacitor structures are fabricated using conventional pulse removal deposition (PLD) techniques. The (100) oriented silicon substrate is first covered with a TiN barrier layer. The substrate covered with TiN is covered with a platinum insulating layer by a PLD process. The ferroelectric layers are grown by PLD in an oxidizing environment at 600 ° C. The ferroelectric loading layer is comprised of a lower contact / template layer of LSCO, a PNZT ferroelectric layer, and a top connection layer of LSCO.

The crystallographic parameters of the thin film of Pb _1-x Nb _x Zr _0.2 Ti _0.8 O ₃ , namely (x / 80/20) PNZT, are given in Table 2.

x (%) c (nm) a (nm) c / a 0 0.4103 0.3968 1.034 6 0.4088 0.3975 1.0284 10 0.4083 0.3991 1.0233

As shown in Fig. 8, the hysteresis curves of the capacitor structures for the three combinations are measured to have a falling voltage of 4.5V. Loop 100 exhibits hysteresis with x = 0. That is, PZT; loop 102 with x = 6%; And loop 104 with x = 10%. The polarization characteristic is slightly reduced when x = 6%, and becomes more substantial when x = 10%. Nevertheless, niobium-rich samples exhibit good hysteresis characteristics.

Similar hysteresis characteristics are obtained using a barrier layer of (Ti _0.9 Al _0.1 ) N containing various niobium. Close interpretation of these curves shows interesting results as the maximum applied voltage is reduced and the devices are weakened. In Fig. 9 the curves for the switched polarized light ΔP = P * −P ＾ are shown as a function of the maximum applied voltage Vmax. Curve 110 shows the switching polarization for Nb inclusion when x = 0%. ; Curve 112 is x = 6%; And curve 114 when x = 10%. A sample that does not contain Nb, PZT, exhibits the largest switched polarization at the highest switching voltage of 5V. The sample with x = 6% is somewhat reduced, with the most containing niobium reveals minimal switched polarization. At 4V, the difference is much larger. However, as the maximum voltages decrease below 3V, the situation changes. At 2V, the results are equal to 6% and 10%. 10 shows the high voltage Vc as a function of the maximum applied voltage Vmax for the same three values of the Nb content. The first curve 120 is x = 0; Second curve 122 is x = 6%; And the third curve 124 gives a value for the case where x = 10%. Lower values of Vc correspond to lower values of Vsat and lower voltage characteristics.

The fatigue failure results are even more interesting. The memory cells are tired with bipolar pulses of ± 3V at 1MHz. The switched polarizations ± P of their bipolars were measured several times during the fatigue failure cycle, and the results are shown in FIG. First curves 130 provide the switched polarization when x = 0; The second curves 132 are x = 6%; And curves 134 when x = 10%. Without fatigue failure, the cells with lower Nb inclusions show better switched polarization than the cells with x = 10%. However, after extended fatigue failure the cells with x = 0 are significantly less valuable, with better overall results with a content of Nb of 6%.

Thus, the La or Nb content must level commercially various ferroelectric memory cells above those generally recommended. In PLZT, when the Zr fraction is about 20%, the lanthanum fraction should be at least 3%, preferably at least 6% and at most 12%. If reasonable polarization is performed, 15% is the maximum of the desired La fraction. The largest value of the La fraction is limited by the formation of PLZT in the non-ferroelectric phase. If the La fraction is much less, preferably about 2%, the Zr polarization can be increased by 50%.

The same numbers in PNZT apply to Zr and Nb polarizations. Expressed by the tetragonal element c / a, it should be reduced to less than 1.029 in the PNZT, preferably less than 1.025. With the PNZT tetragonal component, we expect the beneficial results to extend the range to be reduced to 1.020.

The current memory cell indicated in FIG. 1 is presented to illustrate the precise structure used in the examples above. Crystallographically other structures of directional ferroelectrics can also be used. More preferably any such as incorporating an internal metal barrier disclosed by U.S. Patent Application 08 / 582,545 filed Jan. 3, 1996, and U.S. Patent Application 08 / 871,059, filed June 19,1997 by Dot et al. Platinum is not required either. The former corresponds to PCT application WO97 / 25745.

Although the present invention has been described with respect to particular composites of PLZT and PNZT, it is not limited thereto. Rare earths other than lanthanum and niobium can be used with fractions that reduce tetragonality with respect to fractions that produce higher polarization effects.

Thus, the present invention exchanges unnecessary polarization with the required stress reduction, providing a ferroelectric cell with less fatigue breakdown and higher switching speed.

Claims (16)

A metal oxide first electrode; A ferroelectric layer having a gray titaniumite crystal structure and formed on the first electrode composed of Pb, Zr, Ti, O and at least one additional rare earth element; A second electrode formed on the ferroelectric layer; And A circuit device having a maximum DC power supply voltage of less than 3V and connected to the two electrodes for power, control, and reading of charge stored on the ferroelectric layer, And the ferroelectric layer comprises at least one rare earth element in a fraction sufficient for the circuitry to operate at the maximum DC power supply voltage. The ferroelectric memory cell of claim 1, wherein the at least one rare earth element is La. The ferroelectric memory cell of claim 1, wherein the at least one rare earth element is Nb. 2. The ferroelectric memory cell of claim 1, wherein the fraction x of the rare earth element versus the fraction 1-x of lead is at least 3%. 5. The ferroelectric memory cell of claim 4, wherein the fraction x is at least 6%. 5. The ferroelectric memory cell of claim 4, wherein the fraction x is less than 30%. A first electrode comprising a metal oxide; A ferroelectric layer having a gray titanium crystal structure and composed of Pb _1-x Nb _x Zr _y Ti _1-y O ₃ , wherein x is 3% or more; And And a second electrode formed on the ferroelectric layer. 6. The ferroelectric cell of claim 5, wherein y is between 15% and 30%. 3. The ferroelectric cell of claim 2, wherein y is about 20%. 10. The ferroelectric cell of claim 9, wherein x is at least 6%. The ferroelectric cell of claim 10, wherein x is less than 15%. A first electrode comprising a metal oxide; A first gray titanium formed on the first electrode and including a first positive first rare earth element, a second positive second rare earth element, at least one cation element, and oxygen, together with the first tetragonal element A ferroelectric layer forming a stone crystal structure; And A second electrode formed on the ferroelectric layer, The first and second quantities are values in which the first tetragonal element is less than the second tetragonal element when the ferroelectric layer is formed in the second ashite crystal structure without any of the first rare earth elements. And wherein the first polarization characteristic of the first ashite crystal structure is less than the second at least one corresponding second polarization characteristics. 13. The method of claim 12, wherein the first amount and the second amount, the first tetragonal element is a third when the ferroelectric layer is formed in the third ashite crystal structure without any second rare earth element A ferroelectric cell, selected to have a value less than a tetragonal element, wherein the first polarization of the first tartanite crystal structure is less than the second at least one corresponding third polarization characteristics. 13. The circuit of claim 12, further comprising circuitry having a maximum DC power supply voltage of less than 3V and connected to the two electrodes for powering, charge control, and readout charges stored on the ferroelectric layer. Ferroelectric cell. 13. The ferroelectric cell of claim 12, wherein the ferroelectric layer comprises Pb, La, Zr, Ti, and O. 13. The ferroelectric cell of claim 12, wherein the ferroelectric layer comprises Pb, Nb, Zr, Ti, and O.