MX2015014230A - Dispositivo de procesamiento de datos y metodo de procesamiento de datos. - Google Patents
Dispositivo de procesamiento de datos y metodo de procesamiento de datos.Info
- Publication number
- MX2015014230A MX2015014230A MX2015014230A MX2015014230A MX2015014230A MX 2015014230 A MX2015014230 A MX 2015014230A MX 2015014230 A MX2015014230 A MX 2015014230A MX 2015014230 A MX2015014230 A MX 2015014230A MX 2015014230 A MX2015014230 A MX 2015014230A
- Authority
- MX
- Mexico
- Prior art keywords
- data processing
- group
- code
- ldpc
- ldpc code
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6522—Intended application, e.g. transmission or communication standard
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2626—Arrangements specific to the transmitter only
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Optimization (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Algebra (AREA)
- Multimedia (AREA)
- Computing Systems (AREA)
- Computer Networks & Wireless Communication (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
La presente tecnología se refiere a un dispositivo de procesamiento de datos y un método de procesamiento de datos que puede asegurar la calidad de comunicación excelente en la transmisión de datos usando un código LDPC. En la intercalación en forma de grupo, la intercalación de un código LDPC que tiene una longitud N de código de 64800 bitios y una tasa r de codificación de 5/15 se realiza en una unidad de un grupo de bitios de 360 bitios. En la desintercalación en forma de grupo, una disposición del código LDPC que ha experimentado la intercalación en forma de grupo se regresa a una disposición original. La presente tecnología se puede aplicar a un caso de transmisión de datos usando el código LDPC.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014030012A JP2015156530A (ja) | 2014-02-19 | 2014-02-19 | データ処理装置、及び、データ処理方法 |
PCT/JP2015/053181 WO2015125612A1 (ja) | 2014-02-19 | 2015-02-05 | データ処理装置、及び、データ処理方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
MX2015014230A true MX2015014230A (es) | 2016-03-01 |
MX349019B MX349019B (es) | 2017-07-07 |
Family
ID=53878122
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2015014230A MX349019B (es) | 2014-02-19 | 2015-02-05 | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
Country Status (8)
Country | Link |
---|---|
US (2) | USRE49243E1 (es) |
EP (1) | EP3110010A4 (es) |
JP (1) | JP2015156530A (es) |
KR (1) | KR101716607B1 (es) |
CN (2) | CN105103455B (es) |
CA (1) | CA2908893C (es) |
MX (1) | MX349019B (es) |
WO (1) | WO2015125612A1 (es) |
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GB201312243D0 (en) * | 2013-07-08 | 2013-08-21 | Samsung Electronics Co Ltd | Non-Uniform Constellations |
WO2015041075A1 (ja) * | 2013-09-20 | 2015-03-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
MX2016003551A (es) * | 2013-09-26 | 2016-07-21 | Sony Corp | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
MX2016003553A (es) * | 2013-09-26 | 2016-07-21 | Sony Corp | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
KR101884273B1 (ko) | 2014-02-20 | 2018-08-30 | 상하이 내셔널 엔지니어링 리서치 센터 오브 디지털 텔레비전 컴퍼니, 리미티드 | Ldpc 코드워드 인터리빙 매핑 방법 및 디인터리빙 디매핑 방법 |
KR102287620B1 (ko) * | 2015-02-16 | 2021-08-10 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 2/15인 ldpc 부호어 및 1024-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
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JP6930375B2 (ja) * | 2017-10-31 | 2021-09-01 | ソニーグループ株式会社 | 送信装置及び送信方法 |
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US9191256B2 (en) * | 2012-12-03 | 2015-11-17 | Digital PowerRadio, LLC | Systems and methods for advanced iterative decoding and channel estimation of concatenated coding systems |
US9813191B2 (en) * | 2014-02-05 | 2017-11-07 | Samsung Electronics Co., Ltd. | Transmitting apparatus and modulation method thereof |
US9602137B2 (en) * | 2014-02-19 | 2017-03-21 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
US9602136B2 (en) * | 2014-03-06 | 2017-03-21 | Electronics And Telecommunications Research Institute | Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same |
JP6424888B2 (ja) | 2014-05-21 | 2018-11-21 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
-
2014
- 2014-02-19 JP JP2014030012A patent/JP2015156530A/ja active Pending
-
2015
- 2015-02-05 US US16/381,936 patent/USRE49243E1/en active Active
- 2015-02-05 CN CN201580000538.5A patent/CN105103455B/zh active Active
- 2015-02-05 WO PCT/JP2015/053181 patent/WO2015125612A1/ja active Application Filing
- 2015-02-05 CA CA2908893A patent/CA2908893C/en active Active
- 2015-02-05 KR KR1020157027452A patent/KR101716607B1/ko active IP Right Grant
- 2015-02-05 CN CN201910878189.7A patent/CN110545109B/zh active Active
- 2015-02-05 EP EP15751810.1A patent/EP3110010A4/en not_active Withdrawn
- 2015-02-05 MX MX2015014230A patent/MX349019B/es active IP Right Grant
- 2015-02-05 US US14/782,740 patent/US9621191B2/en not_active Ceased
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CA2908893A1 (en) | 2015-08-27 |
US9621191B2 (en) | 2017-04-11 |
CN105103455A (zh) | 2015-11-25 |
JP2015156530A (ja) | 2015-08-27 |
CA2908893C (en) | 2021-11-16 |
CN105103455B (zh) | 2019-10-01 |
KR20160122627A (ko) | 2016-10-24 |
MX349019B (es) | 2017-07-07 |
CN110545109B (zh) | 2023-02-24 |
USRE49243E1 (en) | 2022-10-11 |
CN110545109A (zh) | 2019-12-06 |
EP3110010A4 (en) | 2017-11-01 |
WO2015125612A1 (ja) | 2015-08-27 |
KR101716607B1 (ko) | 2017-03-14 |
US20160043740A1 (en) | 2016-02-11 |
EP3110010A1 (en) | 2016-12-28 |
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