MX2016003548A - Dispositivo de procesamiento de datos y metodo de procesamiento de datos. - Google Patents
Dispositivo de procesamiento de datos y metodo de procesamiento de datos.Info
- Publication number
- MX2016003548A MX2016003548A MX2016003548A MX2016003548A MX2016003548A MX 2016003548 A MX2016003548 A MX 2016003548A MX 2016003548 A MX2016003548 A MX 2016003548A MX 2016003548 A MX2016003548 A MX 2016003548A MX 2016003548 A MX2016003548 A MX 2016003548A
- Authority
- MX
- Mexico
- Prior art keywords
- data processing
- group
- ldpc code
- code
- processing device
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
- H04L1/0003—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate by switching between different modulation schemes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L2001/0092—Error control systems characterised by the topology of the transmission link
- H04L2001/0093—Point-to-multipoint
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- General Physics & Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Algebra (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Quality & Reliability (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
- Materials For Photolithography (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
Esta tecnología pertenece a un dispositivo de procesamiento de datos y a un método de procesamiento de datos que hace posible asegurar una buena calidad de comunicación cuando se utiliza un código de LDPC para transmitir datos. En el intercalado por grupos, un código de LDPC que tiene una longitud de código de 64,800 bits y una tasa de código de 6/15, 7/15, 8/15, o 9/15 se intercala en una base por grupo de bits, cada grupo de bits tiene 360 bits de longitud. En el desintercalado por grupos, el código de LDPC desintercalado se restablece al orden original del mismo. Esta tecnología puede aplicarse, por ejemplo, para transmisión de datos o similares utilizando un código de LDPC.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013199085 | 2013-09-26 | ||
PCT/JP2014/074196 WO2015045897A1 (ja) | 2013-09-26 | 2014-09-12 | データ処理装置、及びデータ処理方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
MX2016003548A true MX2016003548A (es) | 2016-07-21 |
Family
ID=52743039
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2016003548A MX2016003548A (es) | 2013-09-26 | 2014-09-12 | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
Country Status (8)
Country | Link |
---|---|
US (1) | US20160211868A1 (es) |
EP (1) | EP3051704A4 (es) |
JP (1) | JPWO2015045897A1 (es) |
KR (1) | KR20160064086A (es) |
CN (1) | CN105556856A (es) |
CA (1) | CA2924773A1 (es) |
MX (1) | MX2016003548A (es) |
WO (1) | WO2015045897A1 (es) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102104937B1 (ko) * | 2013-06-14 | 2020-04-27 | 삼성전자주식회사 | Ldpc 부호의 부호화 장치, 그의 부호화 방법, 복호화 장치 및 그의 복호화 방법 |
WO2015016666A1 (en) * | 2013-08-01 | 2015-02-05 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals |
US20160211866A1 (en) * | 2013-09-20 | 2016-07-21 | Sony Corporation | Data processing device and data processing method |
KR20160061330A (ko) * | 2013-09-26 | 2016-05-31 | 소니 주식회사 | 데이터 처리 장치 및 데이터 처리 방법 |
KR20160064087A (ko) * | 2013-09-26 | 2016-06-07 | 소니 주식회사 | 데이터 처리 장치 및 데이터 처리 방법 |
JP2015156532A (ja) * | 2014-02-19 | 2015-08-27 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015170912A (ja) * | 2014-03-05 | 2015-09-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015179960A (ja) | 2014-03-19 | 2015-10-08 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
US20160164540A1 (en) | 2014-05-21 | 2016-06-09 | Sony Corporation | Data processing device and data processing method |
KR102453474B1 (ko) | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
WO2016137254A1 (ko) | 2015-02-27 | 2016-09-01 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
KR101800415B1 (ko) | 2015-03-02 | 2017-11-23 | 삼성전자주식회사 | 송신 장치 및 그의 패리티 퍼뮤테이션 방법 |
US10326474B2 (en) | 2015-03-02 | 2019-06-18 | Samsung Electronics Co., Ltd. | Transmitter and parity permutation method thereof |
KR102553322B1 (ko) * | 2015-04-20 | 2023-07-10 | 한국전자통신연구원 | 레이어드 디비전 멀티플렉싱을 이용한 방송 신호 프레임 생성 장치 및 방송 신호 프레임 생성 방법 |
US20160336968A1 (en) * | 2015-05-11 | 2016-11-17 | Comtech Ef Data Corp. | System and method for encoding and decoding using a plurality of constellations within a single fec block |
US9787326B2 (en) * | 2015-05-19 | 2017-10-10 | Samsung Electronics Co., Ltd. | Method and apparatus for encoding and decoding low density parity check codes |
CN110233701B (zh) * | 2019-05-25 | 2021-11-19 | 西南电子技术研究所(中国电子科技集团公司第十研究所) | 无线通信物理层通信安全的编解码方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3875693B2 (ja) * | 2004-03-24 | 2007-01-31 | 株式会社東芝 | Lpc符号を用いた符号化ビットのマッピング方法及び送信装置 |
KR20060016059A (ko) * | 2004-08-16 | 2006-02-21 | 삼성전자주식회사 | 가변 블록 길이를 가지는 블록 저밀도 패리티 검사 부호부호화/복호 장치 및 방법 |
US7543197B2 (en) * | 2004-12-22 | 2009-06-02 | Qualcomm Incorporated | Pruned bit-reversal interleaver |
US7673225B2 (en) * | 2005-06-21 | 2010-03-02 | Samsung Electronics Co., Ltd. | Apparatus and method for transmitting/receiving data in a communication system using structured low density parity check code |
TWI538415B (zh) * | 2007-11-26 | 2016-06-11 | Sony Corp | Data processing device and data processing method |
CN101488819B (zh) * | 2008-01-15 | 2013-02-27 | 华为技术有限公司 | 一种低密度奇偶校验码编码调制方法及装置 |
EP2134051A1 (en) * | 2008-06-13 | 2009-12-16 | THOMSON Licensing | An adaptive QAM transmission scheme for improving performance on an AWGN channel |
JP5630278B2 (ja) * | 2010-12-28 | 2014-11-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
JP5664919B2 (ja) * | 2011-06-15 | 2015-02-04 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
EP2560311A1 (en) * | 2011-08-17 | 2013-02-20 | Panasonic Corporation | Cyclic-block permutations for spatial multiplexing with quasi-cyclic LDPC codes |
KR20160064087A (ko) * | 2013-09-26 | 2016-06-07 | 소니 주식회사 | 데이터 처리 장치 및 데이터 처리 방법 |
MX2016003557A (es) * | 2013-09-26 | 2016-07-21 | Sony Corp | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
JP2015170912A (ja) * | 2014-03-05 | 2015-09-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015179960A (ja) * | 2014-03-19 | 2015-10-08 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
US10419023B2 (en) * | 2014-03-20 | 2019-09-17 | Electronics And Telecommunications Research Institute | Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 1024-symbol mapping, and bit interleaving method using same |
KR102287620B1 (ko) * | 2015-02-16 | 2021-08-10 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 2/15인 ldpc 부호어 및 1024-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
KR102287623B1 (ko) * | 2015-02-16 | 2021-08-10 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 4/15인 ldpc 부호어 및 1024-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
US10340954B2 (en) * | 2015-05-19 | 2019-07-02 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
US9680505B2 (en) * | 2015-05-19 | 2017-06-13 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
-
2014
- 2014-09-12 CN CN201480051403.7A patent/CN105556856A/zh active Pending
- 2014-09-12 CA CA2924773A patent/CA2924773A1/en not_active Abandoned
- 2014-09-12 US US14/914,125 patent/US20160211868A1/en not_active Abandoned
- 2014-09-12 JP JP2015539101A patent/JPWO2015045897A1/ja not_active Abandoned
- 2014-09-12 WO PCT/JP2014/074196 patent/WO2015045897A1/ja active Application Filing
- 2014-09-12 MX MX2016003548A patent/MX2016003548A/es unknown
- 2014-09-12 EP EP14848286.2A patent/EP3051704A4/en not_active Withdrawn
- 2014-09-12 KR KR1020167006516A patent/KR20160064086A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
EP3051704A1 (en) | 2016-08-03 |
CA2924773A1 (en) | 2015-04-02 |
KR20160064086A (ko) | 2016-06-07 |
WO2015045897A1 (ja) | 2015-04-02 |
US20160211868A1 (en) | 2016-07-21 |
JPWO2015045897A1 (ja) | 2017-03-09 |
EP3051704A4 (en) | 2017-06-21 |
CN105556856A (zh) | 2016-05-04 |
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