MX2019015119A - Dispositivo de procesamiento de datos y metodo de procesamiento de datos. - Google Patents
Dispositivo de procesamiento de datos y metodo de procesamiento de datos.Info
- Publication number
- MX2019015119A MX2019015119A MX2019015119A MX2019015119A MX2019015119A MX 2019015119 A MX2019015119 A MX 2019015119A MX 2019015119 A MX2019015119 A MX 2019015119A MX 2019015119 A MX2019015119 A MX 2019015119A MX 2019015119 A MX2019015119 A MX 2019015119A
- Authority
- MX
- Mexico
- Prior art keywords
- data processing
- group
- code
- ldpc
- ldpc code
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
- H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
- H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
- H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Algebra (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
La presente tecnología se refiere a un dispositivo de procesamiento de datos y un método de procesamiento de datos que puede garantizar una alta calidad de la comunicación en la transmisión de datos usando códigos de LDPC. En la intercalación en forma de grupos, un código de LDPC que tiene un código de longitud N de 64800 bitios, y una tasa r de codificación de 9/15 es intercalada en una unidad de un grupo de bitios de 360 bitios. En la intercalación en forma de grupos, una secuencia de grupos de bitios del código LDPC que han sido sometidos a la intercalación en forma de grupos se devuelve a una secuencia original. La presente tecnología puede ser aplicada a, por ejemplo, un caso en donde la transmisión de datos se realiza usando los códigos de LDPC.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014030014A JP2015156532A (ja) | 2014-02-19 | 2014-02-19 | データ処理装置、及び、データ処理方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
MX2019015119A true MX2019015119A (es) | 2020-02-12 |
Family
ID=53878124
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2016010443A MX2016010443A (es) | 2014-02-19 | 2015-02-05 | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
MX2019015119A MX2019015119A (es) | 2014-02-19 | 2016-08-11 | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2016010443A MX2016010443A (es) | 2014-02-19 | 2015-02-05 | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
Country Status (6)
Country | Link |
---|---|
US (3) | US20170187392A1 (es) |
JP (1) | JP2015156532A (es) |
KR (5) | KR101752343B1 (es) |
CA (1) | CA2939481C (es) |
MX (2) | MX2016010443A (es) |
WO (1) | WO2015125614A1 (es) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102091889B1 (ko) * | 2013-02-08 | 2020-04-14 | 소니 주식회사 | 데이터 처리 장치, 및 데이터 처리 방법 |
JP2015156532A (ja) * | 2014-02-19 | 2015-08-27 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015170912A (ja) * | 2014-03-05 | 2015-09-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015179960A (ja) * | 2014-03-19 | 2015-10-08 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
WO2017085971A1 (ja) * | 2015-11-19 | 2017-05-26 | ソニー株式会社 | 装置、方法及びプログラム |
JP6930376B2 (ja) * | 2017-10-31 | 2021-09-01 | ソニーグループ株式会社 | 送信装置及び送信方法 |
JP6930375B2 (ja) * | 2017-10-31 | 2021-09-01 | ソニーグループ株式会社 | 送信装置及び送信方法 |
JP6930377B2 (ja) * | 2017-10-31 | 2021-09-01 | ソニーグループ株式会社 | 送信装置及び送信方法 |
JP6930374B2 (ja) * | 2017-10-31 | 2021-09-01 | ソニーグループ株式会社 | 送信装置及び送信方法 |
US10354717B1 (en) * | 2018-05-10 | 2019-07-16 | Micron Technology, Inc. | Reduced shifter memory system |
DE102019200256B4 (de) * | 2019-01-10 | 2020-07-30 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verschachteler |
US11032023B1 (en) * | 2019-05-21 | 2021-06-08 | Tarana Wireless, Inc. | Methods for creating check codes, and systems for wireless communication using check codes |
CN113708776B (zh) * | 2020-05-20 | 2023-06-09 | 中国科学院上海高等研究院 | 基于ldpc码的编码方法、系统、介质及装置 |
CN113708777B (zh) * | 2020-05-20 | 2023-06-13 | 中国科学院上海高等研究院 | 基于ldpc码的编码方法、系统、介质及装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7334181B2 (en) | 2003-09-04 | 2008-02-19 | The Directv Group, Inc. | Method and system for providing short block length low density parity check (LDPC) codes |
CN1983861B (zh) * | 2005-06-21 | 2012-09-26 | 三星电子株式会社 | 通信系统中发送/接收数据的装置和方法 |
JP5273054B2 (ja) | 2007-11-26 | 2013-08-28 | ソニー株式会社 | データ処理装置、及びデータ処理方法、並びに、符号化装置、及び符号化方法 |
EP2134051A1 (en) | 2008-06-13 | 2009-12-16 | THOMSON Licensing | An adaptive QAM transmission scheme for improving performance on an AWGN channel |
JP5664919B2 (ja) * | 2011-06-15 | 2015-02-04 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
KR20150005853A (ko) * | 2013-07-05 | 2015-01-15 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
WO2015041482A1 (en) * | 2013-09-18 | 2015-03-26 | Samsung Electronics Co., Ltd. | Transmitting apparatus and puncturing method thereof |
MX2016003548A (es) * | 2013-09-26 | 2016-07-21 | Sony Corp | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
US10396822B2 (en) * | 2013-09-26 | 2019-08-27 | Samsung Electronics Co., Ltd. | Transmitting apparatus and signal processing method thereof |
US10355714B2 (en) * | 2013-10-04 | 2019-07-16 | Samsung Electronics Co., Ltd. | Transmitting apparatus and signal processing method thereof |
JP2015156534A (ja) * | 2014-02-19 | 2015-08-27 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015156532A (ja) * | 2014-02-19 | 2015-08-27 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2015170912A (ja) * | 2014-03-05 | 2015-09-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
-
2014
- 2014-02-19 JP JP2014030014A patent/JP2015156532A/ja active Pending
-
2015
- 2015-02-05 KR KR1020167020548A patent/KR101752343B1/ko active IP Right Grant
- 2015-02-05 KR KR1020197026865A patent/KR102189466B1/ko active IP Right Grant
- 2015-02-05 KR KR1020177017207A patent/KR101929407B1/ko active IP Right Grant
- 2015-02-05 WO PCT/JP2015/053183 patent/WO2015125614A1/ja active Application Filing
- 2015-02-05 MX MX2016010443A patent/MX2016010443A/es active IP Right Grant
- 2015-02-05 US US15/118,331 patent/US20170187392A1/en not_active Abandoned
- 2015-02-05 CA CA2939481A patent/CA2939481C/en active Active
- 2015-02-05 KR KR1020187035768A patent/KR102023155B1/ko active IP Right Grant
- 2015-02-05 KR KR1020207034975A patent/KR102361969B1/ko active IP Right Grant
-
2016
- 2016-08-11 MX MX2019015119A patent/MX2019015119A/es unknown
-
2018
- 2018-04-04 US US15/945,361 patent/US10425112B2/en active Active
-
2019
- 2019-08-15 US US16/541,658 patent/US10979080B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2015156532A (ja) | 2015-08-27 |
KR20200140397A (ko) | 2020-12-15 |
WO2015125614A1 (ja) | 2015-08-27 |
KR101752343B1 (ko) | 2017-06-29 |
KR102361969B1 (ko) | 2022-02-14 |
KR20180133951A (ko) | 2018-12-17 |
US20180302107A1 (en) | 2018-10-18 |
MX2016010443A (es) | 2016-09-22 |
KR102189466B1 (ko) | 2020-12-11 |
CA2939481C (en) | 2021-09-14 |
KR20160121514A (ko) | 2016-10-19 |
KR101929407B1 (ko) | 2018-12-14 |
CA2939481A1 (en) | 2015-08-27 |
KR20190108194A (ko) | 2019-09-23 |
US20170187392A1 (en) | 2017-06-29 |
US10979080B2 (en) | 2021-04-13 |
KR102023155B1 (ko) | 2019-09-20 |
US20190372601A1 (en) | 2019-12-05 |
KR20170075815A (ko) | 2017-07-03 |
US10425112B2 (en) | 2019-09-24 |
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