MX2016000458A - Dispositivo de procesamiento de datos y metodo de procesamiento de datos. - Google Patents
Dispositivo de procesamiento de datos y metodo de procesamiento de datos.Info
- Publication number
- MX2016000458A MX2016000458A MX2016000458A MX2016000458A MX2016000458A MX 2016000458 A MX2016000458 A MX 2016000458A MX 2016000458 A MX2016000458 A MX 2016000458A MX 2016000458 A MX2016000458 A MX 2016000458A MX 2016000458 A MX2016000458 A MX 2016000458A
- Authority
- MX
- Mexico
- Prior art keywords
- data processing
- group
- ldpc code
- processing device
- processing method
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
- H03M13/356—Unequal error protection [UEP]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Multimedia (AREA)
- Computer Networks & Wireless Communication (AREA)
- Error Detection And Correction (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
Esta técnica se relaciona con un dispositivo de procesamiento de datos y un método de procesamiento de datos que hacen posible asegurar una buena calidad de comunicación en transmisión de datos utilizando un código de LDPC. En el intercalado por grupos, un código de LDPC que tiene una longitud de código (N) de 64800 bits y una tasa de código (r) de 6/15, 7/15, 8/15 o 9/15 se intercala con respecto a cada grupo de bits de 360 bits. En el desintercalado por grupos, la disposición del código de LDPC después del intercalado por grupos se regresa a una disposición original. Esta técnica puede aplicarse, por ejemplo, a un caso en donde se realiza transmisión de datos utilizando un código de LDPC.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014104810 | 2014-05-21 | ||
PCT/JP2015/063254 WO2015178216A1 (ja) | 2014-05-21 | 2015-05-08 | データ処理装置、及び、データ処理方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
MX2016000458A true MX2016000458A (es) | 2016-04-28 |
MX362019B MX362019B (es) | 2019-01-04 |
Family
ID=54553889
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2016000458A MX362019B (es) | 2014-05-21 | 2015-05-08 | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
Country Status (7)
Country | Link |
---|---|
US (2) | US20160164540A1 (es) |
EP (1) | EP3148090A4 (es) |
JP (1) | JP6428650B2 (es) |
CN (1) | CN105379127A (es) |
CA (1) | CA2917822A1 (es) |
MX (1) | MX362019B (es) |
WO (1) | WO2015178216A1 (es) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB201312243D0 (en) * | 2013-07-08 | 2013-08-21 | Samsung Electronics Co Ltd | Non-Uniform Constellations |
JP6425100B2 (ja) | 2014-05-21 | 2018-11-21 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP6428649B2 (ja) | 2014-05-21 | 2018-11-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
EP3148085B1 (en) * | 2014-05-21 | 2021-02-24 | Sony Corporation | Bit interleaved coded modulation with a group-wise interleaver adapted to a rate 10/15 ldpc code of length 16200 |
EP3148088B1 (en) | 2014-05-21 | 2021-03-03 | Sony Corporation | Bit interleaved coded modulation with a group-wise interleaver adapted to a rate 12/15 ldpc code of length 16200 |
MX2016000453A (es) | 2014-05-21 | 2016-08-12 | Sony Corp | Dispositivo de procesamiento de datos y metodos de procesamiento de datos. |
KR102287625B1 (ko) * | 2015-02-16 | 2021-08-10 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 2/15인 ldpc 부호어 및 4096-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
US9787326B2 (en) * | 2015-05-19 | 2017-10-10 | Samsung Electronics Co., Ltd. | Method and apparatus for encoding and decoding low density parity check codes |
US10389387B2 (en) * | 2015-05-19 | 2019-08-20 | Sony Semiconductor Solutions Corporation | Coding device and coding method for a DVB-like LDPC code and a LDPC code in an ETRI format |
JP6852427B2 (ja) | 2017-02-06 | 2021-03-31 | ソニー株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP6852428B2 (ja) | 2017-02-06 | 2021-03-31 | ソニー株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP6880792B2 (ja) | 2017-02-06 | 2021-06-02 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
WO2018150939A1 (ja) * | 2017-02-20 | 2018-08-23 | ソニー株式会社 | 送信方法、及び、受信装置 |
WO2018150938A1 (ja) * | 2017-02-20 | 2018-08-23 | ソニー株式会社 | 送信方法、及び、受信装置 |
WO2018150937A1 (ja) * | 2017-02-20 | 2018-08-23 | ソニー株式会社 | 送信方法、及び、受信装置 |
JP6895053B2 (ja) * | 2017-02-20 | 2021-06-30 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP6903979B2 (ja) * | 2017-02-20 | 2021-07-14 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP6895052B2 (ja) * | 2017-02-20 | 2021-06-30 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP7302714B2 (ja) * | 2017-05-31 | 2023-07-04 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP6911540B2 (ja) | 2017-05-31 | 2021-07-28 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP6972664B2 (ja) | 2017-05-31 | 2021-11-24 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP7272492B2 (ja) * | 2018-01-18 | 2023-05-12 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP7077628B2 (ja) * | 2018-01-18 | 2022-05-31 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
JP7135344B2 (ja) * | 2018-01-18 | 2022-09-13 | ソニーグループ株式会社 | 送信装置、送信方法、受信装置、及び、受信方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3875693B2 (ja) * | 2004-03-24 | 2007-01-31 | 株式会社東芝 | Lpc符号を用いた符号化ビットのマッピング方法及び送信装置 |
US7555696B2 (en) * | 2004-12-09 | 2009-06-30 | General Instrument Corporation | Method and apparatus for forward error correction in a content distribution system |
EP1737133B1 (en) * | 2005-06-21 | 2009-12-23 | Samsung Electronics Co., Ltd. | Apparatus and method for transmitting/receiving data in a multi-antenna communication system using a structured low density parity check (LDPC) code |
JP5273054B2 (ja) * | 2007-11-26 | 2013-08-28 | ソニー株式会社 | データ処理装置、及びデータ処理方法、並びに、符号化装置、及び符号化方法 |
CN101488819B (zh) * | 2008-01-15 | 2013-02-27 | 华为技术有限公司 | 一种低密度奇偶校验码编码调制方法及装置 |
EP2134051A1 (en) * | 2008-06-13 | 2009-12-16 | THOMSON Licensing | An adaptive QAM transmission scheme for improving performance on an AWGN channel |
JP5601182B2 (ja) * | 2010-12-07 | 2014-10-08 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
JP5664919B2 (ja) | 2011-06-15 | 2015-02-04 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
EP2560311A1 (en) | 2011-08-17 | 2013-02-20 | Panasonic Corporation | Cyclic-block permutations for spatial multiplexing with quasi-cyclic LDPC codes |
KR20150005853A (ko) * | 2013-07-05 | 2015-01-15 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
KR20160061328A (ko) * | 2013-09-26 | 2016-05-31 | 소니 주식회사 | 데이터 처리 장치 및 데이터 처리 방법 |
CA2924777A1 (en) * | 2013-09-26 | 2015-04-02 | Sony Corporation | Data processing device and data processing method |
WO2015045897A1 (ja) * | 2013-09-26 | 2015-04-02 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
CA2924756A1 (en) * | 2013-09-26 | 2015-04-02 | Sony Corporation | Data processing device and data processing method |
JPWO2015045900A1 (ja) * | 2013-09-26 | 2017-03-09 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
JP2015170912A (ja) * | 2014-03-05 | 2015-09-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
EP3148085B1 (en) * | 2014-05-21 | 2021-02-24 | Sony Corporation | Bit interleaved coded modulation with a group-wise interleaver adapted to a rate 10/15 ldpc code of length 16200 |
JP6424836B2 (ja) * | 2014-05-21 | 2018-11-21 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
MX2016000453A (es) * | 2014-05-21 | 2016-08-12 | Sony Corp | Dispositivo de procesamiento de datos y metodos de procesamiento de datos. |
JP6425100B2 (ja) * | 2014-05-21 | 2018-11-21 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
EP3148088B1 (en) * | 2014-05-21 | 2021-03-03 | Sony Corporation | Bit interleaved coded modulation with a group-wise interleaver adapted to a rate 12/15 ldpc code of length 16200 |
JP6428649B2 (ja) * | 2014-05-21 | 2018-11-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
-
2015
- 2015-05-08 MX MX2016000458A patent/MX362019B/es active IP Right Grant
- 2015-05-08 CA CA2917822A patent/CA2917822A1/en not_active Abandoned
- 2015-05-08 WO PCT/JP2015/063254 patent/WO2015178216A1/ja active Application Filing
- 2015-05-08 CN CN201580001352.1A patent/CN105379127A/zh active Pending
- 2015-05-08 EP EP15796531.0A patent/EP3148090A4/en not_active Withdrawn
- 2015-05-08 JP JP2015560880A patent/JP6428650B2/ja not_active Expired - Fee Related
- 2015-05-08 US US14/903,993 patent/US20160164540A1/en not_active Abandoned
-
2018
- 2018-06-13 US US16/007,601 patent/US10498365B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CA2917822A1 (en) | 2015-11-26 |
US10498365B2 (en) | 2019-12-03 |
JPWO2015178216A1 (ja) | 2017-04-20 |
WO2015178216A1 (ja) | 2015-11-26 |
JP6428650B2 (ja) | 2018-11-28 |
US20160164540A1 (en) | 2016-06-09 |
CN105379127A (zh) | 2016-03-02 |
US20190097659A1 (en) | 2019-03-28 |
MX362019B (es) | 2019-01-04 |
EP3148090A4 (en) | 2018-02-21 |
EP3148090A1 (en) | 2017-03-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
MX2016000458A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX2016003557A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX2019015354A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX349019B (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX2019013109A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX2019005297A (es) | Dispositivo y metodo para procesar datos. | |
MX2016014888A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX2016003548A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX2019015119A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX2016003553A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX2016003552A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX2020000292A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX2016003551A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX2019015632A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
EP3206399A4 (en) | Probability updating method for binary arithmetic coding/decoding, and entropy coding/decoding apparatus using same | |
MX2016003576A (es) | Dispositivo de proceso de datos y metodo de proceso de datos. | |
MX2016011779A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
MX357178B (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
PH12019501754A1 (en) | Transmission method and reception device | |
PH12019501759A1 (en) | Transmission method and reception device | |
EP3306844A4 (en) | Unequal error protection-based data transmission method, apparatus and device | |
PH12017501564A1 (en) | Processing time extension for high banwidth wireless communications | |
MX2019015452A (es) | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. | |
PH12019501863A1 (en) | Transmission method and reception device | |
PH12019501862A1 (en) | Transmission method and reception device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG | Grant or registration |