MX2010007597A - Sistema y método para aplicar selectivamente un voltaje negativo a líneas de palabras durante la operación de lectura de un dispositivo de memoria. - Google Patents

Sistema y método para aplicar selectivamente un voltaje negativo a líneas de palabras durante la operación de lectura de un dispositivo de memoria.

Info

Publication number
MX2010007597A
MX2010007597A MX2010007597A MX2010007597A MX2010007597A MX 2010007597 A MX2010007597 A MX 2010007597A MX 2010007597 A MX2010007597 A MX 2010007597A MX 2010007597 A MX2010007597 A MX 2010007597A MX 2010007597 A MX2010007597 A MX 2010007597A
Authority
MX
Mexico
Prior art keywords
memory device
negative voltage
read operation
selectively applying
applying negative
Prior art date
Application number
MX2010007597A
Other languages
English (en)
Inventor
Cheng Zhong
Sei Seung Yoon
Mohamed H Abu-Rahma
Dongkyu Park
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=40568664&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=MX2010007597(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2010007597A publication Critical patent/MX2010007597A/es

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Se describen sistemas y métodos para aplicar selectivamente voltaje negativo a las líneas de palabras durante la operación de lectura del dispositivo de memoria. En una modalidad, un dispositivo de memoria (100) incluye un circuito lógico de líneas de palabra (110) acoplado a una pluralidad de líneas de palabra (108) y adaptado para aplicar selectivamente un voltaje positivo (V) a una línea de palabras seleccionada acoplada a una celda de memoria seleccionada que incluye un dispositivo de unión de túnel magnética (MTJ - magnetic tunnel junction) y para aplicar un voltaje negativo (NV - negative voltage) a las líneas de palabras no seleccionadas.
MX2010007597A 2008-01-11 2009-01-09 Sistema y método para aplicar selectivamente un voltaje negativo a líneas de palabras durante la operación de lectura de un dispositivo de memoria. MX2010007597A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/972,696 US7672175B2 (en) 2008-01-11 2008-01-11 System and method of selectively applying negative voltage to wordlines during memory device read operation
PCT/US2009/030540 WO2009089411A1 (en) 2008-01-11 2009-01-09 System and method of selectively applying negative voltage to wordlines during memory device read operation

Publications (1)

Publication Number Publication Date
MX2010007597A true MX2010007597A (es) 2010-09-28

Family

ID=40568664

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2010007597A MX2010007597A (es) 2008-01-11 2009-01-09 Sistema y método para aplicar selectivamente un voltaje negativo a líneas de palabras durante la operación de lectura de un dispositivo de memoria.

Country Status (10)

Country Link
US (1) US7672175B2 (es)
EP (1) EP2232494A1 (es)
JP (3) JP5502755B2 (es)
KR (2) KR20120130262A (es)
CN (1) CN101911203B (es)
BR (1) BRPI0906774A2 (es)
CA (1) CA2711671C (es)
MX (1) MX2010007597A (es)
RU (1) RU2450372C2 (es)
WO (1) WO2009089411A1 (es)

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US8958263B2 (en) * 2011-06-10 2015-02-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8811093B2 (en) * 2012-03-13 2014-08-19 Silicon Storage Technology, Inc. Non-volatile memory device and a method of operating same
CN103426477A (zh) * 2012-05-18 2013-12-04 北京兆易创新科技股份有限公司 一种NOR Flash 存储器的读方法及装置
CN103578561A (zh) * 2012-07-23 2014-02-12 北京兆易创新科技股份有限公司 一种快闪存储器及其擦除校验方法和装置
US9672885B2 (en) * 2012-09-04 2017-06-06 Qualcomm Incorporated MRAM word line power control scheme
CN103730145A (zh) * 2012-10-15 2014-04-16 北京兆易创新科技股份有限公司 快闪存储器及其电压控制方法
KR102154026B1 (ko) 2013-08-29 2020-09-09 삼성전자주식회사 자기 메모리 장치의 동작 방법
JP6333832B2 (ja) * 2013-09-20 2018-05-30 国立大学法人東北大学 記憶回路
CN105097030A (zh) * 2014-04-25 2015-11-25 北京兆易创新科技股份有限公司 存储器的编程校验方法和编程校验装置
JP6266479B2 (ja) * 2014-09-12 2018-01-24 東芝メモリ株式会社 メモリシステム
JP6271460B2 (ja) * 2015-03-02 2018-01-31 東芝メモリ株式会社 半導体記憶装置
US9905316B2 (en) * 2016-08-01 2018-02-27 Qualcomm Incorporated Efficient sense amplifier shifting for memory redundancy
KR102480013B1 (ko) * 2018-11-26 2022-12-22 삼성전자 주식회사 누설 전류를 보상하는 메모리 장치 및 이의 동작 방법
US20230054577A1 (en) * 2021-08-20 2023-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device

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SU1053638A1 (ru) * 1982-02-08 1994-12-30 В.И. Овчаренко Накопитель для постоянного запоминающего устройства
SU1108915A1 (ru) * 1982-03-04 1997-05-27 В.И. Кольдяев Матричный накопитель для постоянного запоминающего устройства
KR100295150B1 (ko) * 1997-12-31 2001-07-12 윤종용 비휘발성메모리장치의동작방법과상기동작을구현할수있는장치및그제조방법
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Also Published As

Publication number Publication date
EP2232494A1 (en) 2010-09-29
US20090180315A1 (en) 2009-07-16
JP2013137859A (ja) 2013-07-11
CA2711671A1 (en) 2009-07-16
RU2450372C2 (ru) 2012-05-10
KR20120130262A (ko) 2012-11-29
US7672175B2 (en) 2010-03-02
BRPI0906774A2 (pt) 2015-07-14
JP2015092431A (ja) 2015-05-14
JP5701917B2 (ja) 2015-04-15
KR20100097762A (ko) 2010-09-03
JP5502755B2 (ja) 2014-05-28
CA2711671C (en) 2013-12-17
JP2011510424A (ja) 2011-03-31
RU2010133555A (ru) 2012-02-20
WO2009089411A1 (en) 2009-07-16
CN101911203A (zh) 2010-12-08
CN101911203B (zh) 2013-07-17

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