MX2009009488A - Control de potencia de transistor de linea de palabra para la lectura y escritura en una memoria magnetoresistiva de acceso aleatorio de torque de transferencia de giro. - Google Patents
Control de potencia de transistor de linea de palabra para la lectura y escritura en una memoria magnetoresistiva de acceso aleatorio de torque de transferencia de giro.Info
- Publication number
- MX2009009488A MX2009009488A MX2009009488A MX2009009488A MX2009009488A MX 2009009488 A MX2009009488 A MX 2009009488A MX 2009009488 A MX2009009488 A MX 2009009488A MX 2009009488 A MX2009009488 A MX 2009009488A MX 2009009488 A MX2009009488 A MX 2009009488A
- Authority
- MX
- Mexico
- Prior art keywords
- word line
- line transistor
- random access
- access memory
- write
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1657—Word-line or row circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
- Static Random-Access Memory (AREA)
Abstract
Se describen sistemas, circuitos y métodos para controlar el voltaje de línea de palabra en un transistor de línea de palabra en una memoria magnetoresistiva de acceso aleatorio de torque de transferencia de giro (Spin Transfer Torque Magnetoresistive Random Access Memory - STT-MRAM). Puede suministrarse un primer voltaje al transistor de línea de palabra para operaciones de escritura. Un segundo voltaje, que es menor que el primer voltaje, puede suministrarse al transistor de línea de palabra durante las operaciones de lectura.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US89321707P | 2007-03-06 | 2007-03-06 | |
US11/770,839 US7742329B2 (en) | 2007-03-06 | 2007-06-29 | Word line transistor strength control for read and write in spin transfer torque magnetoresistive random access memory |
PCT/US2008/056086 WO2008109768A1 (en) | 2007-03-06 | 2008-03-06 | Word line transistor strength control for read and write in spin transfer torque magnetoresistive random access memory |
Publications (1)
Publication Number | Publication Date |
---|---|
MX2009009488A true MX2009009488A (es) | 2009-09-16 |
Family
ID=39523385
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2009009488A MX2009009488A (es) | 2007-03-06 | 2008-03-06 | Control de potencia de transistor de linea de palabra para la lectura y escritura en una memoria magnetoresistiva de acceso aleatorio de torque de transferencia de giro. |
Country Status (12)
Country | Link |
---|---|
US (1) | US7742329B2 (es) |
EP (1) | EP2126922B1 (es) |
JP (3) | JP2010520576A (es) |
KR (1) | KR101093889B1 (es) |
CN (1) | CN101641746B (es) |
AT (1) | ATE534996T1 (es) |
BR (1) | BRPI0808640B1 (es) |
CA (1) | CA2677920C (es) |
ES (1) | ES2375015T3 (es) |
MX (1) | MX2009009488A (es) |
RU (1) | RU2419894C1 (es) |
WO (1) | WO2008109768A1 (es) |
Families Citing this family (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7973349B2 (en) | 2005-09-20 | 2011-07-05 | Grandis Inc. | Magnetic device having multilayered free ferromagnetic layer |
US7777261B2 (en) * | 2005-09-20 | 2010-08-17 | Grandis Inc. | Magnetic device having stabilized free ferromagnetic layer |
US7782661B2 (en) * | 2007-04-24 | 2010-08-24 | Magic Technologies, Inc. | Boosted gate voltage programming for spin-torque MRAM array |
US7957179B2 (en) | 2007-06-27 | 2011-06-07 | Grandis Inc. | Magnetic shielding in magnetic multilayer structures |
US8159870B2 (en) * | 2008-04-04 | 2012-04-17 | Qualcomm Incorporated | Array structural design of magnetoresistive random access memory (MRAM) bit cells |
KR101493868B1 (ko) * | 2008-07-10 | 2015-02-17 | 삼성전자주식회사 | 자기 메모리 소자의 구동 방법 |
US7894248B2 (en) | 2008-09-12 | 2011-02-22 | Grandis Inc. | Programmable and redundant circuitry based on magnetic tunnel junction (MTJ) |
US7826255B2 (en) * | 2008-09-15 | 2010-11-02 | Seagate Technology Llc | Variable write and read methods for resistive random access memory |
US7755965B2 (en) | 2008-10-13 | 2010-07-13 | Seagate Technology Llc | Temperature dependent system for reading ST-RAM |
US8107280B2 (en) * | 2008-11-05 | 2012-01-31 | Qualcomm Incorporated | Word line voltage control in STT-MRAM |
US8134856B2 (en) * | 2008-11-05 | 2012-03-13 | Qualcomm Incorporated | Data protection scheme during power-up in spin transfer torque magnetoresistive random access memory |
JP5315940B2 (ja) * | 2008-11-06 | 2013-10-16 | 日本電気株式会社 | 磁気ランダムアクセスメモリ |
US20100128519A1 (en) * | 2008-11-25 | 2010-05-27 | Seagate Technology Llc | Non volatile memory having increased sensing margin |
US9728240B2 (en) * | 2009-04-08 | 2017-08-08 | Avalanche Technology, Inc. | Pulse programming techniques for voltage-controlled magnetoresistive tunnel junction (MTJ) |
KR101048351B1 (ko) | 2009-06-08 | 2011-07-14 | 한양대학교 산학협력단 | 자성 메모리의 동작방법 |
US9099181B2 (en) | 2009-08-19 | 2015-08-04 | Grandis, Inc. | Non-volatile static ram cell circuit and timing method |
US8456926B2 (en) | 2010-11-18 | 2013-06-04 | Grandis, Inc. | Memory write error correction circuit |
US8315090B2 (en) | 2010-06-07 | 2012-11-20 | Grandis, Inc. | Pseudo page mode memory architecture and method |
US8625339B2 (en) | 2011-04-11 | 2014-01-07 | Grandis, Inc. | Multi-cell per memory-bit circuit and method |
US8077508B1 (en) * | 2009-08-19 | 2011-12-13 | Grandis, Inc. | Dynamic multistate memory write driver |
US8077501B2 (en) * | 2009-09-11 | 2011-12-13 | Grandis, Inc. | Differential read and write architecture |
US8411493B2 (en) * | 2009-10-30 | 2013-04-02 | Honeywell International Inc. | Selection device for a spin-torque transfer magnetic random access memory |
US20110141802A1 (en) * | 2009-12-15 | 2011-06-16 | Grandis, Inc. | Method and system for providing a high density memory cell for spin transfer torque random access memory |
US8199553B2 (en) * | 2009-12-17 | 2012-06-12 | Hitachi Global Storage Technologies Netherlands B.V. | Multilevel frequency addressable field driven MRAM |
KR101604042B1 (ko) | 2009-12-30 | 2016-03-16 | 삼성전자주식회사 | 자기 메모리 및 그 동작방법 |
US8335101B2 (en) * | 2010-01-21 | 2012-12-18 | Qualcomm Incorporated | Resistance-based memory with reduced voltage input/output device |
US8723557B2 (en) | 2010-06-07 | 2014-05-13 | Grandis, Inc. | Multi-supply symmetric driver circuit and timing method |
EP2405438B1 (en) | 2010-07-07 | 2016-04-20 | Crocus Technology S.A. | Method for writing in a MRAM-based memory device with reduced power consumption |
US8587994B2 (en) * | 2010-09-08 | 2013-11-19 | Qualcomm Incorporated | System and method for shared sensing MRAM |
US8526266B2 (en) * | 2011-01-21 | 2013-09-03 | Qualcomm Incorporated | Row-decoder circuit and method with dual power systems |
KR101312366B1 (ko) | 2011-04-06 | 2013-09-26 | 에스케이하이닉스 주식회사 | 자기 메모리 장치를 위한 라이트 드라이버 회로 및 자기 메모리 장치 |
WO2013043738A1 (en) * | 2011-09-19 | 2013-03-28 | The Regents Of The University Of California | Body voltage sensing based short pulse reading circuit |
KR20130101376A (ko) * | 2012-03-05 | 2013-09-13 | 삼성전자주식회사 | 동적 래치 및 이를 포함하는 데이터 출력 장치 |
US8923041B2 (en) | 2012-04-11 | 2014-12-30 | Everspin Technologies, Inc. | Self-referenced sense amplifier for spin torque MRAM |
KR20130139066A (ko) | 2012-06-12 | 2013-12-20 | 삼성전자주식회사 | 소스라인 전압 발생기를 포함하는 자기 저항 메모리 장치 |
US9672885B2 (en) | 2012-09-04 | 2017-06-06 | Qualcomm Incorporated | MRAM word line power control scheme |
KR20140067254A (ko) | 2012-11-26 | 2014-06-05 | 삼성전자주식회사 | 메모리 시스템과 이의 동작 방법 |
KR101996265B1 (ko) | 2012-12-14 | 2019-07-04 | 삼성전자주식회사 | 공통소스 반도체 메모리 장치 |
US9064552B2 (en) | 2013-02-27 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Word line driver and related method |
US9691464B2 (en) * | 2013-03-15 | 2017-06-27 | Avalanche Technology, Inc. | Fast programming of magnetic random access memory (MRAM) |
US8792269B1 (en) * | 2013-03-15 | 2014-07-29 | Avalanche Technology, Inc. | Fast programming of magnetic random access memory (MRAM) |
JP6333832B2 (ja) * | 2013-09-20 | 2018-05-30 | 国立大学法人東北大学 | 記憶回路 |
US9196582B2 (en) * | 2013-11-22 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Word line coupling prevention using 3D integrated circuit |
KR102212755B1 (ko) | 2014-07-31 | 2021-02-05 | 삼성전자주식회사 | 전압 발생기 및 이를 포함하는 메모리 장치 |
US9734881B2 (en) * | 2015-02-02 | 2017-08-15 | Globalfoundries Singapore Pte. Ltd. | High sensing margin magnetic resistive memory device in which a memory cell read and write select transistors to provide different read and write paths |
US10096361B2 (en) * | 2015-08-13 | 2018-10-09 | Arm Ltd. | Method, system and device for non-volatile memory device operation |
JP6139623B2 (ja) | 2015-09-15 | 2017-05-31 | 株式会社東芝 | 不揮発性半導体メモリ |
US10127961B2 (en) * | 2015-12-09 | 2018-11-13 | Imec Vzw | Three transistor two junction magnetoresistive random-access memory (MRAM) bit cell |
WO2017111851A1 (en) * | 2015-12-24 | 2017-06-29 | Intel Corporation | Memory cells with enhanced tunneling magnetoresistance ratio, memory devices and systems including the same |
US9786343B1 (en) * | 2016-08-30 | 2017-10-10 | International Business Machines Corporation | STT MRAM common source line array bias scheme |
US10224368B2 (en) * | 2017-06-30 | 2019-03-05 | Qualcomm Incorporated | Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path |
US12014770B2 (en) | 2017-10-17 | 2024-06-18 | R&D3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
US11501826B2 (en) | 2017-10-17 | 2022-11-15 | R&D3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
US10236053B1 (en) | 2017-10-17 | 2019-03-19 | R&D 3 Llc | Method and circuit device incorporating time-to-transition signal node sensing |
US11165012B2 (en) | 2018-10-29 | 2021-11-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Magnetic device and magnetic random access memory |
CN112927736B (zh) * | 2019-12-05 | 2023-12-29 | 上海磁宇信息科技有限公司 | 磁性随机存储器之读写电路 |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6034887A (en) | 1998-08-05 | 2000-03-07 | International Business Machines Corporation | Non-volatile magnetic memory cell and devices |
JP2001154844A (ja) | 1999-11-30 | 2001-06-08 | Nec Corp | シングルチップマイクロコンピュータ |
US6563743B2 (en) * | 2000-11-27 | 2003-05-13 | Hitachi, Ltd. | Semiconductor device having dummy cells and semiconductor device having dummy cells for redundancy |
FR2817999B1 (fr) | 2000-12-07 | 2003-01-10 | Commissariat Energie Atomique | Dispositif magnetique a polarisation de spin et a empilement(s) tri-couche(s) et memoire utilisant ce dispositif |
JP2003016777A (ja) | 2001-06-28 | 2003-01-17 | Mitsubishi Electric Corp | 薄膜磁性体記憶装置 |
KR100446616B1 (ko) * | 2001-10-18 | 2004-09-04 | 삼성전자주식회사 | 단일 트랜지스터형 자기 랜덤 액세스 메모리 소자와 그구동 및 제조방법 |
US6839269B2 (en) * | 2001-12-28 | 2005-01-04 | Kabushiki Kaisha Toshiba | Magnetic random access memory |
KR100464536B1 (ko) | 2002-03-22 | 2005-01-03 | 주식회사 하이닉스반도체 | 자기 저항 램 |
JP3884399B2 (ja) | 2003-05-21 | 2007-02-21 | 株式会社東芝 | 磁気記憶装置 |
US7006375B2 (en) | 2003-06-06 | 2006-02-28 | Seagate Technology Llc | Hybrid write mechanism for high speed and high density magnetic random access memory |
US6985385B2 (en) | 2003-08-26 | 2006-01-10 | Grandis, Inc. | Magnetic memory element utilizing spin transfer switching and storing multiple bits |
JP4192060B2 (ja) * | 2003-09-12 | 2008-12-03 | シャープ株式会社 | 不揮発性半導体記憶装置 |
US7009877B1 (en) | 2003-11-14 | 2006-03-07 | Grandis, Inc. | Three-terminal magnetostatically coupled spin transfer-based MRAM cell |
US6999366B2 (en) | 2003-12-03 | 2006-02-14 | Hewlett-Packard Development Company, Lp. | Magnetic memory including a sense result category between logic states |
EP1560221B1 (en) | 2004-01-29 | 2008-09-03 | Sharp Kabushiki Kaisha | Semiconductor memory device |
TW200527656A (en) * | 2004-02-05 | 2005-08-16 | Renesas Tech Corp | Semiconductor device |
JP2006185477A (ja) * | 2004-12-27 | 2006-07-13 | Fujitsu Ltd | 磁気メモリ装置並びにその読み出し方法及び書き込み方法 |
US7190612B2 (en) | 2005-03-31 | 2007-03-13 | Grandis, Inc. | Circuitry for use in current switching a magnetic cell |
US7236391B2 (en) * | 2005-04-22 | 2007-06-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Magnetic random access memory device |
US7289356B2 (en) | 2005-06-08 | 2007-10-30 | Grandis, Inc. | Fast magnetic memory devices utilizing spin transfer and magnetic elements used therein |
JP2007012696A (ja) * | 2005-06-28 | 2007-01-18 | Tdk Corp | 磁気メモリ |
KR100674983B1 (ko) * | 2005-07-13 | 2007-01-29 | 삼성전자주식회사 | 구동전압 레벨을 변경할 수 있는 상 변화 메모리 장치 |
WO2007015358A1 (ja) * | 2005-08-02 | 2007-02-08 | Nec Corporation | 磁気ランダムアクセスメモリ及びその動作方法 |
US7224601B2 (en) | 2005-08-25 | 2007-05-29 | Grandis Inc. | Oscillating-field assisted spin torque switching of a magnetic tunnel junction memory element |
US7272035B1 (en) | 2005-08-31 | 2007-09-18 | Grandis, Inc. | Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells |
US7272034B1 (en) | 2005-08-31 | 2007-09-18 | Grandis, Inc. | Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells |
US7646627B2 (en) * | 2006-05-18 | 2010-01-12 | Renesas Technology Corp. | Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance |
JP4883982B2 (ja) | 2005-10-19 | 2012-02-22 | ルネサスエレクトロニクス株式会社 | 不揮発性記憶装置 |
US7286395B2 (en) | 2005-10-27 | 2007-10-23 | Grandis, Inc. | Current driven switched magnetic storage cells having improved read and write margins and magnetic memories using such cells |
JP5193419B2 (ja) * | 2005-10-28 | 2013-05-08 | 株式会社東芝 | スピン注入磁気ランダムアクセスメモリとその書き込み方法 |
US7187577B1 (en) | 2005-11-23 | 2007-03-06 | Grandis, Inc. | Method and system for providing current balanced writing for memory cells and magnetic devices |
US7430135B2 (en) | 2005-12-23 | 2008-09-30 | Grandis Inc. | Current-switched spin-transfer magnetic devices with reduced spin-transfer switching current density |
JP2007184063A (ja) | 2006-01-10 | 2007-07-19 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
JP2007266498A (ja) | 2006-03-29 | 2007-10-11 | Toshiba Corp | 磁気記録素子及び磁気メモリ |
US7345912B2 (en) | 2006-06-01 | 2008-03-18 | Grandis, Inc. | Method and system for providing a magnetic memory structure utilizing spin transfer |
US7379327B2 (en) | 2006-06-26 | 2008-05-27 | Grandis, Inc. | Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells having enhanced read and write margins |
-
2007
- 2007-06-29 US US11/770,839 patent/US7742329B2/en active Active
-
2008
- 2008-03-06 CN CN2008800070971A patent/CN101641746B/zh active Active
- 2008-03-06 RU RU2009136705/08A patent/RU2419894C1/ru not_active IP Right Cessation
- 2008-03-06 JP JP2009552895A patent/JP2010520576A/ja not_active Withdrawn
- 2008-03-06 WO PCT/US2008/056086 patent/WO2008109768A1/en active Application Filing
- 2008-03-06 AT AT08731574T patent/ATE534996T1/de active
- 2008-03-06 KR KR1020097020770A patent/KR101093889B1/ko active IP Right Grant
- 2008-03-06 BR BRPI0808640-0A patent/BRPI0808640B1/pt not_active IP Right Cessation
- 2008-03-06 CA CA2677920A patent/CA2677920C/en not_active Expired - Fee Related
- 2008-03-06 EP EP08731574A patent/EP2126922B1/en active Active
- 2008-03-06 ES ES08731574T patent/ES2375015T3/es active Active
- 2008-03-06 MX MX2009009488A patent/MX2009009488A/es active IP Right Grant
-
2012
- 2012-10-01 JP JP2012219353A patent/JP5951433B2/ja not_active Expired - Fee Related
-
2014
- 2014-09-16 JP JP2014187867A patent/JP2015043251A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
CN101641746A (zh) | 2010-02-03 |
JP5951433B2 (ja) | 2016-07-13 |
ATE534996T1 (de) | 2011-12-15 |
ES2375015T3 (es) | 2012-02-24 |
CA2677920C (en) | 2013-10-01 |
US20080219043A1 (en) | 2008-09-11 |
US7742329B2 (en) | 2010-06-22 |
BRPI0808640A8 (pt) | 2019-01-15 |
JP2010520576A (ja) | 2010-06-10 |
JP2013048008A (ja) | 2013-03-07 |
KR20090119924A (ko) | 2009-11-20 |
RU2419894C1 (ru) | 2011-05-27 |
EP2126922A1 (en) | 2009-12-02 |
BRPI0808640A2 (pt) | 2014-08-05 |
WO2008109768A1 (en) | 2008-09-12 |
JP2015043251A (ja) | 2015-03-05 |
CN101641746B (zh) | 2012-09-19 |
KR101093889B1 (ko) | 2011-12-13 |
CA2677920A1 (en) | 2008-09-12 |
BRPI0808640B1 (pt) | 2020-01-07 |
EP2126922B1 (en) | 2011-11-23 |
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