KR970077221A - 반도체소자의 콘택홀 형성방법 - Google Patents

반도체소자의 콘택홀 형성방법 Download PDF

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Publication number
KR970077221A
KR970077221A KR1019960018365A KR19960018365A KR970077221A KR 970077221 A KR970077221 A KR 970077221A KR 1019960018365 A KR1019960018365 A KR 1019960018365A KR 19960018365 A KR19960018365 A KR 19960018365A KR 970077221 A KR970077221 A KR 970077221A
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KR
South Korea
Prior art keywords
contact hole
forming
insulating layer
semiconductor device
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KR1019960018365A
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English (en)
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KR100399931B1 (ko
Inventor
김석수
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019960018365A priority Critical patent/KR100399931B1/ko
Publication of KR970077221A publication Critical patent/KR970077221A/ko
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Publication of KR100399931B1 publication Critical patent/KR100399931B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 금속배선간 접속을 위한 콘택홀에서의 금속의 매립성을 향상시키기 위한 콘택홀 형성방법에 관한 것으로, 반도체기판상에 층간절연막을 형성하는 단계와, 상기 층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계와, 상기 콘택홀 측벽에 절연막 스페이서를 형성하는 단계, 및 습식식각에 의해 세정공정을 행하는 단계를 포함하여 이루어지는 반도체소자의 콘택홀 형성방법을 제공한다.

Description

반도체소자의 콘택홀 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 의한 반도체소자의 콘택홀 형성방법을 도시한 공정순서도이다.

Claims (7)

  1. 반도체기판상에 층간절연막을 형성하는 단계와, 상기 층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀 측벽에 절연막 스페이서를 형성하는 단계, 및 습식식각에 의해 세정공정을 행하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.
  2. 제1항에 있어서, 상기 절연막 스페이서는 상기 콘택홀 내부를 포함한 상기 층간절연막 전면에 절연막을 형성한 후, 전면식각을 실시하여 상기 절연막이 콘택홀 측벽에 스페이서 형태로 남도록 하여 형성하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.
  3. 제1항에 있어서, 상기 층간절연막은 제1, 제2 및 제3산화막을 차례로 증착하여 형성하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.
  4. 제3항에 있어서, 상기 제1 및 제3산화막은 동일한 문질을 사용하여 형성하고, 상기 제2산화막은 상기 제1 및 제3산화막과는 다른 물질을 사용하여 형성하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.
  5. 제4항에 있어서, 상기 제1 및 제3산화막은 BPSG로 형성하고, 제2산화막은 HTO, MTO 또는 TEOS로 형성하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.
  6. 제1항에 있어서, 상기 절연막 스페이서는 TEOS, HTO, MTO 또는 BPSG중의 어느 한 산화막으로 형성하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.
  7. 제1항에 있어서, 상기 콘택홀은 원하는 크기보다 상기 절연막 스페이서 폭만큼 크게 형성하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960018365A 1996-05-28 1996-05-28 반도체소자의콘택홀형성방법 KR100399931B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960018365A KR100399931B1 (ko) 1996-05-28 1996-05-28 반도체소자의콘택홀형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960018365A KR100399931B1 (ko) 1996-05-28 1996-05-28 반도체소자의콘택홀형성방법

Publications (2)

Publication Number Publication Date
KR970077221A true KR970077221A (ko) 1997-12-12
KR100399931B1 KR100399931B1 (ko) 2003-12-24

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KR1019960018365A KR100399931B1 (ko) 1996-05-28 1996-05-28 반도체소자의콘택홀형성방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100827511B1 (ko) * 2002-06-29 2008-05-06 주식회사 하이닉스반도체 반도체 소자의 제조 방법

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950021130A (ko) * 1993-12-31 1995-07-26 김주용 반도체 소자의 콘택홀 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100827511B1 (ko) * 2002-06-29 2008-05-06 주식회사 하이닉스반도체 반도체 소자의 제조 방법

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