KR970067707A - 반도체 소자의 제조방법 - Google Patents

반도체 소자의 제조방법 Download PDF

Info

Publication number
KR970067707A
KR970067707A KR1019960009077A KR19960009077A KR970067707A KR 970067707 A KR970067707 A KR 970067707A KR 1019960009077 A KR1019960009077 A KR 1019960009077A KR 19960009077 A KR19960009077 A KR 19960009077A KR 970067707 A KR970067707 A KR 970067707A
Authority
KR
South Korea
Prior art keywords
semiconductor device
tungsten silicide
photoresist pattern
polysilicon layer
manufacturing semiconductor
Prior art date
Application number
KR1019960009077A
Other languages
English (en)
Other versions
KR100187654B1 (ko
Inventor
양성우
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960009077A priority Critical patent/KR100187654B1/ko
Publication of KR970067707A publication Critical patent/KR970067707A/ko
Application granted granted Critical
Publication of KR100187654B1 publication Critical patent/KR100187654B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 제조방법을 제공하는 것으로, 폴리실리콘층을 텅스텐 실리사이드의 상부에 형성하며 텅스텐 실리사이드 및 폴리실리콘층의 일측면을 산화막에 의해 노출되지 않도록 하여 텅스텐 실리사이드의 손상 및 들뜸현상을 방지하므로써 소자의 수율을 향상시킬 수 있는 효과가 있다.

Description

반도체 소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A 내지 2D도는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도

Claims (1)

  1. 반도체 소자의 제조방법에 있어서, 스크라이브 라인의 실리콘기판상에 텅스텐 실리사이드, 폴리실리콘층 및 제1감광막패턴을 순차적으로 형성하는 단계와, 상기 단계로부터 상기 제1감광막 패턴을 마스크로 이용하여 상기 폴리실리콘층 및 텅스텐 실리사이드를 순차적으로 식각하는 단계와, 상기 단계로부터 상기 제1감광막패턴을 제거한 후 상기 실리콘기판의 전체 상부면에 산화막을 형성하는 단계와, 상기 단계로부터 상기 텅스텐 실리사이드 및 폴리실리콘층의 일측면이 노출되지 않도록 상기 산화막상에 제2감광막패턴을 형성하는 단계와, 상기 단계로부터 상기 제2감광막 패턴을 마스크로 이용하여 노출된 산화막을 식각한 후 상기 제2감광막 패턴을 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.
KR1019960009077A 1996-03-29 1996-03-29 반도체 소자의 제조방법 KR100187654B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960009077A KR100187654B1 (ko) 1996-03-29 1996-03-29 반도체 소자의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960009077A KR100187654B1 (ko) 1996-03-29 1996-03-29 반도체 소자의 제조방법

Publications (2)

Publication Number Publication Date
KR970067707A true KR970067707A (ko) 1997-10-13
KR100187654B1 KR100187654B1 (ko) 1999-06-01

Family

ID=19454408

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960009077A KR100187654B1 (ko) 1996-03-29 1996-03-29 반도체 소자의 제조방법

Country Status (1)

Country Link
KR (1) KR100187654B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100632627B1 (ko) * 2000-11-17 2006-10-09 주식회사 하이닉스반도체 반도체 소자의 제조방법

Also Published As

Publication number Publication date
KR100187654B1 (ko) 1999-06-01

Similar Documents

Publication Publication Date Title
KR970013074A (ko) 반도체장치의 평탄화방법 및 이를 이용한 소자분리방법
KR940016687A (ko) 반도체 접속장치 및 그 제조방법
KR970067707A (ko) 반도체 소자의 제조방법
KR980006066A (ko) 반도체 장치의 소자 분리막 형성방법
KR940004779A (ko) 트렌치 기술을 이용한 반도체 장치의 소자분리영역 형성방법
KR950021130A (ko) 반도체 소자의 콘택홀 제조방법
KR980005592A (ko) 자기 정렬 콘택 홀 형성 방법
KR970052290A (ko) 반도체 소자의 제조방법
KR950034415A (ko) 반도체 소자의 미세패턴 제조방법
KR980003891A (ko) 노광용 정렬 키 제조방법
KR970063566A (ko) 반도체소자의 제조방법
KR970023736A (ko) 반도체장치의 콘택부 형성방법
KR970018388A (ko) 에어 버퍼층을 갖는 반도체장치의 제조방법(Method of fabricationg a semiconductor device with an air buffer layer)
KR970067646A (ko) 반도체 소자의 콘택홀 형성방법
KR980005535A (ko) 반도체 소자의 콘택홀 형성방법
KR980003863A (ko) 반도체 소자의 미세패턴 형성방법
KR980005760A (ko) 반도체 장치의 제조방법
KR970017952A (ko) 고체 촬상 소자의 제조공정에 있어서의 정렬키 형성 방법
KR960012324A (ko) 반도체소자의 게이트전극 콘택 및 그 제조방법
KR980005884A (ko) 반도체 디바이스의 트랜지스터 제조방법
KR980005619A (ko) 반도체 소자의 콘택홀 형성방법
KR980006104A (ko) 반도체 소자의 트렌치 아이솔레이션 형성 방법
KR20000019879A (ko) 게이트의 형성방법
KR950025869A (ko) 콘택홀 형성방법
KR940022854A (ko) 반도체장치의 접촉창 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20061211

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee