KR970060456A - 초고주파소자 실장 패키지 및 패키지에 사용되는 본딩와이어의 기생효과 감소방법 - Google Patents
초고주파소자 실장 패키지 및 패키지에 사용되는 본딩와이어의 기생효과 감소방법 Download PDFInfo
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- KR970060456A KR970060456A KR1019970019918A KR19970019918A KR970060456A KR 970060456 A KR970060456 A KR 970060456A KR 1019970019918 A KR1019970019918 A KR 1019970019918A KR 19970019918 A KR19970019918 A KR 19970019918A KR 970060456 A KR970060456 A KR 970060456A
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Abstract
본 발명은 초고주파소자 실장 패키지 및 그 패키지에 사용되는 본딩와이어의 기생 효과를 감소시키는 방법에 관한 것으로, 패키지 공정에서 본딩와이어가 공기중에 노출되는 부분에 비유전율이 3.5∼4.5인 유전체(10)를 몰딩하여 본딩와이어로 인한 기생성분을 감소시키고 정합특성을 개선토록 한 것이다. 몰딩된 이중본딩와이어(7″)를 모멘트법(Method of Moment)을 이용하여 해석하고 기존 본딩방법들의 특성과 비교하였다. 특히, 상기 유전체(FR-4 합성물)(10)의 유전율을 광대역 주파수에서 손실 및 변화를 고려할 수 있는 콜-콜(Cole-Cole) 모델을 이용하여 해석한 결과, 주파수 20GHz에서 기생 리액턴스는 11Ω으로 공기중의 단일 본딩와이어(7), 이 중 본딩와이어(7′) 및 리본 본딩와이어(11)에 비하여 각각 약 90%, 80% 및 60%가 감소하였다. 또한, 등가 특성임피던스는 60Ω으로 공기중의 단일 본딩와이어(7), 이중 본딩와이어(7′) 및 리본 본딩와이어(11)의 235Ω, 133Ω 및 98Ω에 비하여 정합 특성이 크게 개선되었다. 또한, 이러한 정합 특성의 개선으로 20GHz에서 반사손실은 각각 15dB, 10dB 및 5dB이 개선되었고 삽입손실은 각각 2.5dB, 0.7dB 및 0.2dB이 개선되었다. 이러한 발명은 초고속 및 초고주파 소자용 실장 패키지에 응용되어 본딩와이어로 인한 내부소자의 특성저하를 최소화시키는 효과가 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3a도는 본 발명에 의한 초고주파소자의 실장 패키지에서 본딩와이어가 공기중에 노출되는 공간을 유전체로 몰딩한 패키지의 조립 상태를 나타낸 개념도이다.
3b도는 제3a도에서 유전체로 몰딩한 본딩와이어의 특성을 검증하기 위하여 실측 제작한 테스트 패키지의 측면도와 평면도이다.
Claims (10)
- 세라믹 패키지, 금속밀봉 패키지 혹은 플래스틱 패키지 구조를 한 초고주파 소자 실장 패키지의 본딩와이어에서 발생되는 기생성분을 패키지 내부에서 자체적으로 감소시키게 하기 위한 초고주파소자 실장패키지 구조에 있어서, 초고주파 소자 칩(2)의 내부회로와 외부회로 사이를 전기적으로 연결하는 연결선인 본딩와이어가 공기중에 노출되는 공간 부분에 소정의 유전율을 갖는 유전체(10)를 몰딩한 것을 특징으로 하는 초고주파소자 실장패키지.
- 제1항에 있어서, 상기 유전체(10)는 백메탈(1)상에 조립되는 칩(2) 상의 본딩패드(4)와 알루미나(3)측의 리드스트립(5) 간에 연결되어 칩(2) 내부와 외부회로 사이를 전기적으로 연결하는 본딩와이어가 상기 백메탈(1) 상에서 공기중에 노출되는 부분에 몰딩되는 것을 특징으로 하는 초고주파소자 실장패키지.
- 제1항에 있어서, 상기 유전체(10)로 몰딩된 본딩와이어는 반도체 기판 위에 여러개의 모노리딕 집적회로를 접착하고 본딩와이어로 상기 각 모노리딕 집적회로의 본딩패드와 반도체 기판 위에 제작된 미세 도체 선로를 연결하여 다기능 반도체 소자를 구성하는 멀티칩 모듈에서 상기 모듈 내부의 칩과 칩 간을 연결하는 본딩와이어에 적용된 것을 특징으로 하는 초고주파소자 실장패키지.
- 제1항에 있어서, 상기 유전체(10)로 몰딩된 본딩와이어는 다층의 적층 구조를 한 멀티레벨 패키지에서 레벨1의 칩(2)과 패키지의 리드스트립 간을 연결하는 본딩와이어에 적용된 것을 특징으로 하는 초고주파소자 실장패키지.
- 제1항에 있어서, 상기 유전체(10)로 몰딩된 본딩와이어는 다층의 적층 구조를 한 멀티레벨 패키지에서 레벨2의 칩(2)이 조립된 패키지 기판의 리드스트립과 하우징 간을 연결하는 본딩와이어에 적용된 것을 특징으로 하는 초고주파소자 실장패키지.
- 제1항에 있어서, 상기 유전체(10)로 몰딩된 본딩와이어는 다층의 적층 구조를 한 멀티레벨 패키지에서 레벨 3의 칩(2)이 조립된 보드와 하우징의 외부연결 커넥터 간을 연결하는 본딩와이어에 적용된 것을 특징으로 하는 초고주파소자 실장패키지.
- 제1항에 있어서, 상기 유전체(10)로 몰딩된 본딩와이어는 프린트 기판(Printed Circuit Board) 상의 회로 패턴 위에 패키지되지 않은 칩을 접착하는 칩온보드(Chip On Board) 모듈에서 상기 프린트 기판에 접착되는 칩의 본딩패드와 프린트 기판 상의 회로 패턴 간을 연결하는 본딩와이어에 적용된 것을 특징으로 하는 초고주파소자 실장패키지.
- 제1항 내지 제7항에 있어서, 상기 본딩와이어는 이중본딩와이어(7″)인 것을 특징으로 하는 초고주파 실장패키지.
- 제1항 내지 제7항에 있어서, 상기 유전체(10)는 비유전율의 변화 범위가 3.5∼4.5인 FR-4 합성물로 이루어지는 것을 특징으로 하는 초고주파 실장패키지.
- 세라믹 패키지, 금속밀봉 패키지 혹은 플래스틱 패키지 구조를 한 초고주파 소자 실장 패키지의 본딩와이어에서 발생되는 기생성분을 패키지 내부에서 자체적으로 감소시키게 하기 위한 방법에 있어서, 칩(2) 또는 칩(2)이 조립된 패키지가 또 다른 칩(2) 또는 외부회로와 연결되는 연결선인 본딩와이어가 공기중에 노출되는 부분에 소정의 유전율을 갖는 유전체(10)를 채워서 몰딩한 후 60℃에서 수 분간 경화시켜서 초고주파소자 실장패키지의 본딩와이어에서 발생하는 기생효과를 감소시키는 것을 특징으로 하는 초고주파소자 실장패키지의 기생효과 감소방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (2)
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KR1019970019918A KR100270817B1 (ko) | 1997-05-22 | 1997-05-22 | 초고주파소자 실장 패키지 및 그 패키지에 사용되는 본딩와이어의 기생효과 감소방법 |
US09/019,088 US20010015490A1 (en) | 1997-05-22 | 1998-02-05 | High speed digital and microwave device package |
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KR1019970019918A KR100270817B1 (ko) | 1997-05-22 | 1997-05-22 | 초고주파소자 실장 패키지 및 그 패키지에 사용되는 본딩와이어의 기생효과 감소방법 |
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KR970060456A true KR970060456A (ko) | 1997-08-12 |
KR100270817B1 KR100270817B1 (ko) | 2000-11-01 |
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KR (1) | KR100270817B1 (ko) |
Cited By (1)
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KR19990025077A (ko) * | 1997-09-10 | 1999-04-06 | 윤종용 | 인덕터 |
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GB0018643D0 (en) * | 2000-07-31 | 2000-09-13 | Koninkl Philips Electronics Nv | Semiconductor devices |
CA2418683C (en) * | 2003-02-11 | 2007-01-02 | Ibm Canada Limited - Ibm Canada Limitee | Area-array with low inductance connecting device |
US7303113B2 (en) * | 2003-11-28 | 2007-12-04 | International Business Machines Corporation | Method and structure for controlled impedance wire bonds using co-dispensing of dielectric spacers |
DE102005012494A1 (de) * | 2005-03-16 | 2006-09-28 | Shf Communication Technologies Ag | Verbessertes Bondverfahren zur Verbindung von Mikrowellenschaltungen |
DE102005039165B4 (de) * | 2005-08-17 | 2010-12-02 | Infineon Technologies Ag | Draht- und streifengebondetes Halbleiterleistungsbauteil und Verfahren zu dessen Herstellung |
CN101657897B (zh) * | 2007-04-17 | 2012-02-15 | Nxp股份有限公司 | 制造具有应用于微电子封装的导电构件的元件的方法 |
US8436450B2 (en) * | 2008-02-01 | 2013-05-07 | Viasat, Inc. | Differential internally matched wire-bond interface |
JP5343510B2 (ja) * | 2008-10-29 | 2013-11-13 | ミツミ電機株式会社 | 半導体装置 |
KR100950511B1 (ko) | 2009-09-22 | 2010-03-30 | 테세라 리써치 엘엘씨 | 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리 |
KR100935854B1 (ko) | 2009-09-22 | 2010-01-08 | 테세라 리써치 엘엘씨 | 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리 |
US8786083B2 (en) | 2010-09-16 | 2014-07-22 | Tessera, Inc. | Impedance controlled packages with metal sheet or 2-layer RDL |
US9136197B2 (en) | 2010-09-16 | 2015-09-15 | Tessera, Inc. | Impedence controlled packages with metal sheet or 2-layer RDL |
US8581377B2 (en) | 2010-09-16 | 2013-11-12 | Tessera, Inc. | TSOP with impedance control |
US8853708B2 (en) | 2010-09-16 | 2014-10-07 | Tessera, Inc. | Stacked multi-die packages with impedance control |
US8222725B2 (en) | 2010-09-16 | 2012-07-17 | Tessera, Inc. | Metal can impedance control structure |
EP2509105A1 (en) * | 2011-04-04 | 2012-10-10 | Nxp B.V. | Semiconductor device having improved performance for high RF output powers |
US10672703B2 (en) | 2018-09-26 | 2020-06-02 | Nxp Usa, Inc. | Transistor with shield structure, packaged device, and method of fabrication |
US20200098684A1 (en) * | 2018-09-26 | 2020-03-26 | Nxp Usa, Inc. | Transistor, packaged device, and method of fabrication |
JP7426702B2 (ja) | 2020-02-13 | 2024-02-02 | ザインエレクトロニクス株式会社 | 半導体装置 |
CN114019619B (zh) * | 2021-10-26 | 2023-07-04 | 武汉光谷信息光电子创新中心有限公司 | 一种光器件集成的电路结构以及装配方法 |
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JP2689467B2 (ja) * | 1988-03-29 | 1997-12-10 | 日本電気株式会社 | 半導体集積回路装置のパッケージ |
JPH03124052A (ja) * | 1989-10-06 | 1991-05-27 | Nec Corp | 樹脂封止型半導体装置 |
JPH05211252A (ja) * | 1992-01-06 | 1993-08-20 | Nec Corp | 半導体装置の製造方法 |
JPH0945822A (ja) * | 1995-08-03 | 1997-02-14 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
-
1997
- 1997-05-22 KR KR1019970019918A patent/KR100270817B1/ko not_active IP Right Cessation
-
1998
- 1998-02-05 US US09/019,088 patent/US20010015490A1/en not_active Abandoned
Cited By (1)
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KR19990025077A (ko) * | 1997-09-10 | 1999-04-06 | 윤종용 | 인덕터 |
Also Published As
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US20010015490A1 (en) | 2001-08-23 |
KR100270817B1 (ko) | 2000-11-01 |
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