KR970053724A - 무연 땜납을 사용하여 플립-칩(flip-chip)을 상호접속하는 방법 - Google Patents

무연 땜납을 사용하여 플립-칩(flip-chip)을 상호접속하는 방법 Download PDF

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Publication number
KR970053724A
KR970053724A KR1019960054313A KR19960054313A KR970053724A KR 970053724 A KR970053724 A KR 970053724A KR 1019960054313 A KR1019960054313 A KR 1019960054313A KR 19960054313 A KR19960054313 A KR 19960054313A KR 970053724 A KR970053724 A KR 970053724A
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South Korea
Prior art keywords
layer
lead
interconnect structure
solder ball
free solder
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KR1019960054313A
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English (en)
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KR100207888B1 (ko
Inventor
파나요티스 콘스탄티뉴 안드리카코스
마다브 다타
하리클리아 델리기아니
윌마 진 호르칸스
강성곤
케이스 토마스 크위에트니아크
간가드하라 스와미 마사드
삼파스 푸루쇼타만
리덴 시
호-밍 통
Original Assignee
포만 제프리 엘
인터내셔널 비지네스 머신즈 코포레이션
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    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • C22C13/02—Alloys based on tin with antimony or bismuth as the next major constituent
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/01—Layered products comprising a layer of metal all layers being exclusively metallic
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Abstract

본 발명은 패키지(package)에 마이크로전자 소자칩을 접속하는데 적합한 상호접속 구조를 제공한다. 특히, 본 발명은 종종 C4(제어된 컬랩스 칩(collapse chip)접속)라고 하는 영역-어레이(area-array) 또는 플립-칩(flip-chip)기술에 관한 것이다. 상기 구조는 비활성화 기판(예를 들면, 실리콘 웨이퍼(wafer))상에 용착된 접착/장벽층, 임의로 부가적인 접착층, 접착/장벽층상에 Ni, Co, Fe, NiFe, NiCo, CoFe 및 NiCoFe로 이루어진 그룹으로부터 선택되는 금속의 땜납가능한 층, 및 주성분으로서 주석, 및 Bi, Ag 및 Sb로부터 선택되는 하나 이상의 합금원소를 포함하며 또한 임의의 Zn, In, Ni, Co 및 Cu로 이루어진 그룹으로부터 선택되는 하나 이상의 원소를 포함하는 무연(lead-free) 땜납볼(solder ball)을 포함함을 특징으로 한다.

Description

무연 땜납을 사용하여 플립-칩(flip-chip)을 상호접속하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 일반적인 C4구조를 도시한다.

Claims (29)

  1. 마이크로전자 소자칩을 패키지에 플립-칩(flip-chip) 부착시키기에 적합한 상호접속 구조에 있어서, 상기 소자와 땜납가능한 층사이에 있는 접착/장벽층, 및 Ni, Co, Fe, NiFe, NiCo, CoFe 및 NiCoFe로 이루어진 그룹으로부터 선택되는 금속층인 땜납가능한 층을 포함하는 2개층의 볼(ball)한정 금속간 화합물; 및 주성분으로서 주석, 및 Bi, Ag 및 Sb로부터 선택되는 하나 이상의 합금성분을 포함하는, 상기 땜납가능한 층상에 선별적으로 위치한 하나 이상의 무연 땜납볼을 포함함을 특징으로 하는 상호접속 구조.
  2. 제1항에 있어서, 상기 무연 땜납볼의 하나 이상의 합금성분이 Bi 약 1 내지 20%, Ag 1 내지 5% 및 Sb 1 내지 10%의 범위를 갖는 상호접속 구조.
  3. 제2항에 있어서, 상기 무연 땜납볼의 하나 이상의 합금성분이 약 5%의 Bi, 3.5%의 Ag 및 5%의 Sb인 상호접속 구조.
  4. 제1항에 있어서, 상기 무연 땜납볼이 Zn, In, Ni, Co 및 Cu로 이루어진 그룹으로부터 선택되는 하나 이상의 합금성분을 추가로 포함하는 상호접속 구조.
  5. 제4항에 있어서, 상기 무연 땜납볼 합금성분이 Zn 0.5 내지 5%, Ni 0.5 내지 5%, Co 0.5 내지 5%, Cu 0.5 내지 5% 및 In 0.5 내지 10%의 범위인 상호접속 구조.
  6. 제1항에 있어서, 상기 땜납가능한 층의 조성이 20%이상이 Fe이고, 그 나머지가 Ni인 상호접속 구조.
  7. 제6항에 있어서, 상기 땜납가능한 층의 조성이 약 50%가 Fe이고, 약 50%가 Ni인 상호접속 구조.
  8. 제5항에 있어서, 상기 땜납볼이 Sn-3.5Ag, Sn-5Bi, Sn-5Sb; Sn-3.5Ag-1Cu, Sn-5Bi-1Cu, Sn-5Sb-1Cu, Sn-3.5Ag-2In, Sn-3.5Ag-1Zn; Sn-5Bi-2In, Sn-5Bi-2Ag, Sn-5Sb-2In, Sn-5Bi-2Ag, Sn-5Sb-1Zn; Sn-3.5Ag-2In-1Cu, Sn-3.5Ag-2In-1Ni, Sn-5Bi-2In-1Ag, Sn-5Bi-2In-1Cu; 및 Sn-5Bi-2In-1Ni, Sn-5Sb-2Ag-1Cu, Sn-5Sb-2Ag-1Cu, Sn-5Sb-2Ag-1Ni로 이루어진 그룹으로부터 선택되는 금속 합금을 포함하는 상호접속 구조.
  9. 제1항에 있어서, 상기 접착/장벽층이 Cr 및 TiW로부터 선택되는 금속인 상호접속 구조.
  10. 마이크로전자 소자칩을 패키지에 플립-칩 부착시키기에 적합한 상호접속 구조에 있어서, 상기 소자와 상기 접착층사이에 있는 접착/장벽층, 접착/장벽층의 상부에 있는 접착층, 및 Ni, Co, Fe, NiFe, CoFe 및 NiCoFe로 이루어진 그룹으로부터 선택되는 금속층인, 상기 접착층의 상부에 있는 땜납가능한 층을 포함하는 3개층의 볼 한정 금속간 화합물; 및 주성분으로서의 주석, 및 Bi, Ag 및 Sb로부터 선택되는 하나 이상의 합금성분을 포함하는, 상기땜납가능한 층상에 선별적으로 위치한 하나 이상의 무연 땜납볼을 포함함을 특징으로 하는 상호접속 구조.
  11. 제10항에 있어서, 상기 무연 땜납볼의 상기 하나이상의 합금성분이 Bi 약 1 내지 20%, Ag 1 내지 5% 및 Sb 1 내지 10%의 범위를 갖는 상호접속 구조.
  12. 제11항에 있어서, 상기 무연 땜납볼의 합금성분이 약 5%의 Bi, 3.5%의 Ag 및 5%의 Sb인 상호접속 구조.
  13. 제10항에 있어서, 상기 무연 땜납볼이 Zn, In, Ni, Co 및 Cu로 이루어진 그룹으로부터 선택되는 하나이상의 합금성분을 추가로 포함하는 상호접속 구조.
  14. 제13항에 있어서, 상기 무연 땜납볼 합금성분이 Zn 0.5 내지 5%, Ni 0.5 내지 5%, Co 0.5 내지 5%, Cu 0.5 내지 5%, In 0.5 내지 10%의 범위인 상호접속 구조.
  15. 제10항에 있어서, 상기 땜납가능한 층의 조성이 20%이상이 Fe이고, 그 나머지가 Ni인 상호접속 구조.
  16. 제15항에 있어서, 상기 땜납가능한 층의 조성이 약 50%가 Fe이고, 약 50%가 Ni인 상호접속 구조.
  17. 제14항에 있어서, 상기 땜납볼이 Sn-3.5Ag, Sn-5Bi, Sn-5Sb; Sn-3.5Ag-1Cu, Sn-5Bi-1Cu, Sn-5Sb-1Cu, Sn-3.5Ag-2In, Sn-3.5Ag-1Zn; Sn-5Bi-2In, Sn-5Bi-2Ag, Sn-5Sb-2In, Sn-5Bi-2Ag, Sn-5Sb-1Zn; Sn-3.5Ag-2In-1Cu, Sn-3.5Ag-2In-1Ni, Sn-5Bi-2In-1Ag, Sn-5Bi-2In-1Cu; 및 Sn-5Bi-2In-1Ni, Sn-5Sb-2Ag-2In, Sn-5Sb-2Ag-1Cu, Sn-5Sb-2Ag-1Ni로 이루어진 그룹으로부터 선택되는 금속 합금을 상기 땜납볼이 포함하는 상호접속 구조.
  18. 제10항에 있어서, 부가적인 접착층이 접착/장벽층과의 경계면에서는 Cr함량이 높고 땜납가능한 층과의 경계면에서는 Cu함량이 높은 동시용착된 Cr 및 Cu를 포함하는 상으로된 CrCu물질인 상호접속 구조.
  19. 제10항에 있어서, 상기 접착층이 Cr 및 TiW로부터 선택된 금속인 상호접속 구조.
  20. a) 비활성화 웨이퍼상에 접착/장벽층을 용착시키고; b) 상기 장벽층에 직접 접촉시키기 위해 땜납가능한 층을 용착시키고; c) 최소한 도금된 땜납패드의 두께만큼 큰 두께를 갖는 포토레지스트(photoresist)를 사용하여 상기 웨이퍼상에 상호접속 패턴을 한정시키고; d) 마스크를 통해 무연 땜납층을 용착시키고; e) 포토레지스트를 제거하고; f) 장벽층 및 땜납가능한 층의 선별적인 에칭에 의해 볼 한정 금속간 화합물을 형성시키고; g) 땜납을 재유동시킴을 포함함을 특징으로하는, 마이크로전자 소자칩을 플립-칩 결합시키기 위한 상호접속 구조를 제조하는 방법.
  21. 제20항에 있어서, 상기 무연 땜납볼의 하나이상의 합금성분이 Bi 약 1 내지 20%, Ag 1 내지 5% 및 Sb 1 내지 10%의 범위를 갖는 방법.
  22. 제21항에 있어서, 상기 무연 땜납볼의 합금성분이 약 5%의 Bi, 3.5%의 Ag 및 5%의 Sb인 방법.
  23. 제20항에 있어서, 상기 무연 땜납볼이 Zn, In, Ni, Co 및 Cu로 이루어진 그룹으로부터 선택되는 하나이상의 합금성분을 추가로 포함하는 방법.
  24. 제23항에 있어서, 상기 무연 땜납볼 합금성분이 Zn 0.5 내지 5%, Ni 0.5 내지 5%, Co 0.5 내지 5%, Cu 0.5 내지 5% 및 In 0.5 내지 10%의 범위인 방법.
  25. 제20항에 있어서, 상기 땜납가능한 층의 조성이 20%이상이 Fe이고, 그 나머지가 Ni인 방법.
  26. 제25항에 있어서, 상기 땜납가능한 층의 조성이 약 50%가 Fe이고, 약 50%가 Ni인 방법.
  27. 제24항에 있어서, 상기 땜납볼이 Sn-3.5Ag, Sn-5Bi, Sn-5Sb; Sn-3.5Ag-1Cu, Sn-5Bi-1Cu, Sn-5Sb-1Cu, Sn-3.5Ag-2In, Sn-3.5Ag-1Zn; Sn-5Bi-2In, Sn-5Bi-2Ag, Sn-5Sb-2In, Sn-5Bi-2Ag, Sn-5Sb-1Zn; Sn-3.5Ag-2In-1Cu, Sn-3.5Ag-2In-1Ni, Sn-5Bi-2In-1Ag, Sn-5Bi-2In-1Cu; 및 Sn-5Bi-2In-1Ni, Sn-5Sb-2Ag-2In, Sn-5Sb-2Ag-1Cu, Sn-5Sb-2Ag-1Ni로 이루어진 그룹으로부터 선택되는 금속 합금을 상기 땜납볼이 포함하는 방법.
  28. 제20항에 있어서, 상기 접착/장벽층이 Cr 및 TiW로부터 선택된 금속인 방법.
  29. 제20항에 있어서, 상기 접착/장벽층과 상기 땜납가능한 층사이에 부가적인 접착층을 용착시키는 단계를 추가로 포함하고, 상기 선별적인 에칭 단계가 상기 접착/장벽층, 상기 접착층 및 상기 땜납가능한 층을 포함하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960054313A 1995-12-22 1996-11-15 무연 땜납을 사용하여 플립-칩을 상호접속하는 방법 KR100207888B1 (ko)

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US60/009,183 1995-12-22
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US08/614,984 US6224690B1 (en) 1995-12-22 1996-03-12 Flip-Chip interconnections using lead-free solders
US8/614,984 1996-03-12

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