KR970013040A - 반도체소자 제조방법 - Google Patents

반도체소자 제조방법 Download PDF

Info

Publication number
KR970013040A
KR970013040A KR1019950025944A KR19950025944A KR970013040A KR 970013040 A KR970013040 A KR 970013040A KR 1019950025944 A KR1019950025944 A KR 1019950025944A KR 19950025944 A KR19950025944 A KR 19950025944A KR 970013040 A KR970013040 A KR 970013040A
Authority
KR
South Korea
Prior art keywords
resist layer
pattern
forming
substrate
semiconductor device
Prior art date
Application number
KR1019950025944A
Other languages
English (en)
Other versions
KR0161917B1 (ko
Inventor
정기응
Original Assignee
구자홍
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, 엘지전자 주식회사 filed Critical 구자홍
Priority to KR1019950025944A priority Critical patent/KR0161917B1/ko
Priority to US08/692,534 priority patent/US5658826A/en
Publication of KR970013040A publication Critical patent/KR970013040A/ko
Application granted granted Critical
Publication of KR0161917B1 publication Critical patent/KR0161917B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자 제조방법에 간한 것으로, 반도체소자의 게이트길이를 감소시키고, 저항을 줄이기 위한 것이다. 본 발명은 기판상에 제1레지스트층을 형성하는 단계와, 상기 제1레지스트층을 전자빔에 의해 선택적으로 노광 및 현상하여 제1폭을 갖는 패턴을 형성하는 단계, 상기 기판 전면에 절연막을 형성하는 단계, 상기 절연막상에 제2레지스트층을 형성하는 단계, 상기 제2레지스트층을 UV 리스그래피공정에 의해 선택적으로 노광 및 현상하여 상기 제1레지스트층 패턴 상부에 제2폭의 패턴을 형성하는 단계, 상기 절연막의 노출된 부위를 건식식삭하는 단계, 기판상에 게이트 형성용 금속을 증착하는 단계, 리프트오프공정에 의해 상기 제1레지스트층 및 제2레지스트층을 제거하여 T자형 게이트를 형성하는 단계로 이루어지는 반도체소자 제조방법을 제공한다.

Description

반도체소자 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 T형 게이트 형성방법을 도시한 공정순서도.

Claims (4)

  1. 기판상에 제1레지스트층을 형성하는 단계와, 상기 제1레지스트층을 전자빔에 의해 선택적으로 노광 및 현상하여 제1폭을 갖는 패턴을 형성하는 단계, 상기 기판 전면에 절연막을 형성하는 단계, 상기 절연막상에 제2레지스트층을 형성하는 단계, 상기 제2레지스트층을 UV 리스그래피공정에 의해 선택적으로 노광 및 현상하여 상기 제1레지스트층 패턴 상부에 제2폭의 패턴을 형성하는 단계, 상기 절연막의 노출된 부위를 건식식삭하는 단계, 기판상에 게이트 형성용 금속을 증착하는 단계, 및 리프트오프공정에 의해 상기 제1레지스트층 및 제2레지스트층을 제거하여 T자형 게이트를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체소자 제조방법.
  2. 제1항에 있어서, 상기 제1레지스트층은 PMMA를 도포하여 형성하는 것을 특징으로 하는 반도체소자 제조방법.
  3. 제1항에 있어서, 상기 제2레지스트층은 페턴은 1-2㎛정도의 폭으로 형성하는 것을 특징으로 하는 반도체소자 제조방법.
  4. 제1항에 있어서, 상기 제1레지스트층은 패턴은 적어도 0.2㎛정도의 폭을 가지도록 형상하는 것을 특징으로 하는 반도체소자 제조방법.
KR1019950025944A 1995-08-22 1995-08-22 반도체소자 제조방법 KR0161917B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019950025944A KR0161917B1 (ko) 1995-08-22 1995-08-22 반도체소자 제조방법
US08/692,534 US5658826A (en) 1995-08-22 1996-08-06 Method for fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950025944A KR0161917B1 (ko) 1995-08-22 1995-08-22 반도체소자 제조방법

Publications (2)

Publication Number Publication Date
KR970013040A true KR970013040A (ko) 1997-03-29
KR0161917B1 KR0161917B1 (ko) 1999-02-01

Family

ID=19424082

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950025944A KR0161917B1 (ko) 1995-08-22 1995-08-22 반도체소자 제조방법

Country Status (2)

Country Link
US (1) US5658826A (ko)
KR (1) KR0161917B1 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3539652B2 (ja) * 1996-08-28 2004-07-07 シャープ株式会社 フォトマスクの製造方法
US6159781A (en) * 1998-10-01 2000-12-12 Chartered Semiconductor Manufacturing, Ltd. Way to fabricate the self-aligned T-shape gate to reduce gate resistivity
US6284613B1 (en) 1999-11-05 2001-09-04 Chartered Semiconductor Manufacturing Ltd. Method for forming a T-gate for better salicidation
US6877213B2 (en) * 2002-01-07 2005-04-12 International Business Machines Corporation Feature size reduction in thin film magnetic head using low temperature deposition coating of photolithographically-defined trenches
US6770209B2 (en) 2002-01-09 2004-08-03 International Business Machines Corporation Isotropic deposition for trench narrowing of features to be created by reactive ion etch processing
CN103065953B (zh) * 2012-12-26 2015-06-24 中国电子科技集团公司第五十五研究所 一种利用电镀工艺在GaN材料上制备细栅的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2664736B2 (ja) * 1988-08-30 1997-10-22 株式会社東芝 半導体装置用電極の形成方法
JPH04223342A (ja) * 1990-12-26 1992-08-13 Mitsubishi Electric Corp 半導体装置のゲート電極とその製造方法
JP2740050B2 (ja) * 1991-03-19 1998-04-15 株式会社東芝 溝埋込み配線形成方法
EP0592064B1 (en) * 1992-08-19 1998-09-23 Mitsubishi Denki Kabushiki Kaisha Method of producing a field effect transistor
JPH0786310A (ja) * 1993-09-20 1995-03-31 Mitsubishi Electric Corp 高融点金属ゲート電極の形成方法

Also Published As

Publication number Publication date
US5658826A (en) 1997-08-19
KR0161917B1 (ko) 1999-02-01

Similar Documents

Publication Publication Date Title
KR100348902B1 (ko) 에이치이엠티의 감마게이트 제조방법
KR970013040A (ko) 반도체소자 제조방법
KR0128827B1 (ko) 위상반전마스크 제조방법
KR950015647A (ko) 반도체장치의 제조방법
KR930018661A (ko) 콘택트홀의 형성방법
KR950015617A (ko) 반도체소자의 미세패턴 제조방법
KR970008372A (ko) 반도체장치의 미세 패턴 형성방법
KR950021146A (ko) 이중노광에 의한 t-형 게이트의 제조방법
KR960006695B1 (ko) 다중마스크에 의한 미세콘택홀 형성방법
KR0165465B1 (ko) 단차를 갖는 구조물상에 균일한 콘택형성방법
KR960006564B1 (ko) 반도체 소자의 미세 패턴 형성방법
KR950025484A (ko) 반도체 제조용 마스크의 크롬패턴 형성방법
KR970013063A (ko) 반도체소자의 미세패턴 형성방법
KR970013064A (ko) 반도체소자의 미세패턴 형성방법
KR970016754A (ko) 반도체 장치용 마스크 제조방법
KR960035921A (ko) 전계효과트랜지스터 제조방법
KR970054538A (ko) T-형 게이트 형성방법
KR950021045A (ko) 반도체 소자의 미세 패턴 형성방법
KR970006549A (ko) 전기 도금에 의한 메탈층 형성 방법
KR980005764A (ko) 2층 이상의 금속층을 패터닝하는 식각방법
KR960026304A (ko) 반도체 소자의 패턴 형성방법
KR960026635A (ko) 금속배선 형성방법
KR950006981A (ko) 포토레지스트패턴 형성방법
KR970051843A (ko) 반도체 장치의 감광막 패턴 형성방법
KR980003882A (ko) 위상반전 마스크 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080618

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee