KR970003875A - 와이어본드 없는 모듈 패키지와 그 제조방법 - Google Patents

와이어본드 없는 모듈 패키지와 그 제조방법 Download PDF

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KR970003875A
KR970003875A KR1019960018381A KR19960018381A KR970003875A KR 970003875 A KR970003875 A KR 970003875A KR 1019960018381 A KR1019960018381 A KR 1019960018381A KR 19960018381 A KR19960018381 A KR 19960018381A KR 970003875 A KR970003875 A KR 970003875A
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conductive material
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semiconductor die
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엘. 로메로 길레르모
제이. 앤더슨 사무엘
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빈센트 비. 인그라시아
모토로라 인코포레이티드
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Abstract

본 발명은 다수의 포켓을 한정하는 AIN 기판을 내부에 갖는 캐비티를 가진 다공성 Sic의 성형된 프리폼을 포함하는 와이어본드 없는 모듈 패키지와 그 제조방법을 제공한다. 프리폼에는 Al이 침투되고, Al은 각각의 포켓내에 증착된다. 반도체 다이는 한 포켓내의 Al상에 장착된다. 유전체 층은 Al을 덮고, 알루미늄과 다이에의 접속부를 노출시키기 위해 위치되고 유전체 층을 관통하는 구멍을 한정한다. 전도성 재료는 단자와 다이와 단자 사이에 상호접속부를 한정하기 위해 다이 Al과 접촉되는 유전체 층상에 위치된다.

Description

와이어본드 없는 모듈 패키지와 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제9도는 본 발명에 따른 와이어본드 없는 모듈 패키지의 제조 공정에 있어서 여러가지 단계를 설명하는 사시도.

Claims (5)

  1. 와이어본드 없는 모듈 패키지의 제조방법에 있어서, 내부에 한정된 캐비티를 가진 프리폼을 제공하는 단계와, 상기 캐비티를 다수의 개별 영역으로 분할하는 유전체 격벽을 캐비티내에 제공하는 단계와, 상기 유전체 격벽은 제1전도성 재료의 각각의 부분을 제1전도성 재료의 모든 다른 부분으로부터 전기적으로 절연시키는데, 상기 제1전도성 재료의 다수의 부분중의 각각의 부분을 다수의 영역의 각각에 위치시키는 단계와, 상기 다수의 영역중의 한 영역내의 상기 제1전도성 재료의 제1부분상에 반도체 다이를 장착시키는 단계와, 상기 전도성 재료의 다수의 부분상에 외부 단자를 형성하는 단계와, 상기 다이로부터 외부 단자에의 전기 접속부를 한정하는 금속층을 증착하는 단계를 포함하는 것을 특징으로 하는 와이어본드 없는 모듈 패키지의 제조방법.
  2. 와이어본드 없는 모듈 패키지의 제조방법에 있어서, 내부에 한정된 캐비티를 가진 프리폼을 제공하는 단계와, 상기 캐비티를 다수의 개별 영역으로 분할하는 유전체 격벽을 캐비티내에 제공하는 단계와, 상기 유전체 격벽은 제1전도성 재료의 각각의 부분을 제1전도성 재료의 모든 다른 부분으로부터 전기적으로 절연시키는데, 상기 제1전도성 재료의 다수의 부분중의 각각의 부분을 다수의 영역의 각각에 위치시키는 단계와, 상기 다수의 영역중의 한 영역내의 상기 제1전도성 재료의 제1부분상에 반도체 다이를 장착시키는 단계와, 유전체층은 그 층을 관통하여 한정되고 상기 제1전도성 재료의 부분의 표면을 노출시키며 상기 반도체 다이에의 접속부를 노출시키기 위해서 위치된 구멍을 갖는데, 상기 유전체 층을 상기 다수의 영역의 각각의 영역내의 상기 제1전도성 재료의 다수의 부분 위에 위치시키는 단계와, 외부 단자와 상기 반도체 다이와 외부 단자 사이에 상호 접속부를 한정하기 위해서, 상기 반도체 다이와 상기 제1전도성 재료의 부분의 노출된 표면에의 접속부에 접촉하도록 상기 유전체 층상에 제2전도성 재료의 부분을 위치시키는 단계를 포함하는 것을 특징으로 하는 와이어본드 없는 모듈 패키지의 제조 방법.
  3. 와이어본드 없는 모듈 패키지의 제조방법에 있어서, 내부에 한정된 캐비티를 가진 실리콘 탄화물의 성형된 프리폼을 제공하는 단계와, 내부에 한정된 다수의 포켓을 가진 세라믹 기판을 제공하고, 상기 캐비티를 다수의 개별 영역으로 분할하기 위해서 외향 개방되는 포켓을 가진 기판을 캐비티 내에 위치시키는 단계와, 상기 기판의 포켓은 각각의 개별 영역내의 알루미늄을 침투시키고, 다수의 개별 영역의 각각의 영역내에 알루미늄을 증착시키는 단계와, 상기 다수의 영역중의 한 영역내에 알루미늄상에 반도체 다이를 장착시키는 단계와, 유전체 층은 그 층을 관통하여 한정되고 상기 알루미늄의 표면을 노출시키고 상기 반도체 다이의 접속부를 노출시키기 위해서 위치된 구멍을 갖는데, 상기 유전체 층을 상기 다수의 영역의 각각의 영역내의 알루미늄 위에 위치시키는 단계와, 외부 단자와 상기 반도체 다이와 외부 단자 사이에 상호접속부를 한정하기 위해서, 상기 반도체 다이와 상기 알루미늄의 노출된 표면에의 접속부에 접촉하도록 상기 유전체 층상에 전도성 재료의 부분을 위치시키는 단계를 포함하는 것을 특징으로 하는 와이어본드 없는 모듈패키지의 제조방법.
  4. 와이어본드 없는 모듈 패키지에 있어서, 내부에 한정된 캐비티를 가진 프리폼과, 상기 캐비티를 다수의 개별 영역으로 분할하며 캐비티내의 위치된 유전체 격벽과, 상기 유전체 격벽은 제1전도성 재료의 각각의 부분을 제1전도성 재료의 모든 다른 부분으로부터 전기적으로 절연시키는데, 상기 다수의 개별 영역의 각각의 영역에 각각 위치된 상기 제1전도성 재료의 다수의 부분과, 상기 다수의 영역중의 한 영역내의 상기 제1전도성 재료의 제1부분상에 장착된 반도체 다이와, 상기 제1전도성 재료의 다수의 부분상에 한정된 외부 단자와, 상기 반도체 다이와 외부단자 사이에 연장되어 상호접속부를 제공하는 금속 증착부를 포함하는 것을 특징으로 하는 와이어본드 없는 모듈 패키지.
  5. 와이어본드 없는 모듈 패키지에 있어서, 내부에 한정된 캐비티를 가진 프리폼과, 상기 캐비티를 다수의 개별 영역으로 분할하며, 캐비티내에 위치된 유전체 격벽과, 상기 유전체 격벽은 제1전도성 재료의 각각의 부분을 제1전도성 재료의 모든 다른 부분으로부터 전기적으로 절연시키는데, 상기 다수의 개별 영역의 각각의 영역에 각각 위치된 상기 제1전도성 재료의 다수의 부분과, 상기 다수의 영역중의 한 영역내의 상기 제1전도성 재료의 제1부분상에 장착된 반도체 다이와, 유전체 층은 그 층을 관통하여 한정되고 상기 제1전도성 재료의 부분의 표면을 노출시키며 상기 반도체 다이에의 접속부를 노출시키기 위해서 위치된 구멍을 갖는데, 상기 다수의 영역의 각각의 영역내의 상기 제1전도성 재료의 다수의 부분 위에 위치된 상기 유전체 층과, 외부 단자와 상기 반도체 다이와 외부 단자 사이에 상호 접속부를 한정하며, 상기 반도체 다이와 상기 제1전도성 재료의 부분의 노출된 표면에의 접속부에 접촉하도록 상기 유전체 층상에 위치된 제2전도성 재료의 부분을 포함하는 것을 특징으로 하는 와이어본드 없는 모듈 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960018381A 1995-06-05 1996-05-29 와이어본드없는모듈패키지와그제조방법 KR100418318B1 (ko)

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EP0747949A3 (en) 1998-04-29
US5616886A (en) 1997-04-01
KR100418318B1 (ko) 2004-04-28
EP0747949A2 (en) 1996-12-11
JPH08335665A (ja) 1996-12-17

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