KR960043114A - 반도체 소자의 금속배선 형성방법 - Google Patents

반도체 소자의 금속배선 형성방법 Download PDF

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KR960043114A
KR960043114A KR1019950010977A KR19950010977A KR960043114A KR 960043114 A KR960043114 A KR 960043114A KR 1019950010977 A KR1019950010977 A KR 1019950010977A KR 19950010977 A KR19950010977 A KR 19950010977A KR 960043114 A KR960043114 A KR 960043114A
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South Korea
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forming
trench
film
metal wiring
interlayer insulating
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KR1019950010977A
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KR100223284B1 (ko
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김천수
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김주용
현대전자산업 주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882Reflowing or applying of pressure to better fill the contact hole
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53219Aluminium alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 형성방법에 관하여 개시된다.
본 발명은 금속배선이 형성될 부분에 트랜치를 형성하고, 낮은 리플로우 온도를 갖는 전도물질과 화학 기계적 연마공정에 의해 효과적으로 금속배선을 형성할 수 있다.
따라서, 본 발명은 금속배선 형성과 더불어 표면 평탄화를 이루므로써, 반도체 소자의 고집적화를 가능하게 하며, 소자의 제조 수율을 향상시킨다.

Description

반도체 소자의 금속배선 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A 내지 1I도는 본 발명에 의한 반도체 소자의 금속배선 형성단계를 도시한 소자의 단면도.

Claims (5)

  1. 반도체 소자의 금속배선 형성방법에 있어서, 반도체 기판상에 제1층간 절연막을 형성하고, 표면 평탄화를 위하여 상기 제1층간 절연막을 화학 기계적 연마 공정으로 연마하는 단계와, 상기 제1층간 절연막상에 제1질화막을 얇게 형성하고, 상기 제1질화막상에 제1산화막을 형성하는 단계와, 제1금속배선이 형성될 부분의 상기 제1산화막 및 상기 제1질화막을 순차적으로 식각하여 제1트랜치를 형성하는 단계와, 상기 제1트랜치를 포함한 상기 제1산화막상에 제1티타늄층을 얇게 형성하고, 상기 제1티타늄층상에 제1도전층을 형성한 후, 리플로우 공정을 실시하는 단계와, 상기 제1도전층을 화학 기계적 연마공정으로 상기 제1산화막이 충분히 노출될 때까지 연마하여 상기 제1트랜치내에만 상기 제1도전층을 남겨 제1금속배선을 형성하는 단계와, 상기 제1금속배선 및 상기 제1산화막상에 제2층간 절연막을 형성하고, 상기 제2층간 절연막상에 제2질화막을 얇게 형성한 후, 그 상부에 제2산화막을 형성하는 단계와, 제2금속배선이 형성될 부분의 상기 제2산화막을 식각하여 제2트랜치를 형성하는 단계와, 비아홀 마스크를 사용한 리소그라피 공정 및 식각공정으로 상기 제2트랜치의 소정부분 아래의 상기 제2질화막과 상기 제2층간 절연막을 식각하여 비아홀을 형성하는 단계와, 상기 제2트랜치 및 상기 비아홀을 포함한 상기 제2산화막상에 제2티타늄층을 얇게 형성하고, 상기 제2티타늄층상에 제2도전층을 형성한 후, 리플로우 공정을 실시하는 단계와, 상기 제2도전층을 화학 기계적 연마공정으로 상기 제2신화막이 충분히 노출될 때까지 연마하여 상기 제2트랜치 및 비아홀내에만 상기 제2도전층을 남겨 제2금속배선을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금배선 형성방법.
  2. 제1항에 있어서, 상기 제1 및 2산화막 각각은 상기 제1 및 제2금속배선 각각의 두께를 고려하여 형성되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  3. 제1항에 있어서, 상기 제1 및 2도전층은 A1-1%Ge-0.5%Cu의 알루미늄 합금인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  4. 제1항에 있어서, 상기 리플로우 공정은 400 내지 450℃의 저온에서 150 내지 200초간의 열처리로 실시되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  5. 제1항에 있어서, 상기 제1 및 2도전층의 화학 기계적 연마공정은 0.2㎛/min 정도의 연마비로 실시되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950010977A 1995-05-04 1995-05-04 반도체 소자의 금속배선 형성방법 KR100223284B1 (ko)

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KR1019950010977A KR100223284B1 (ko) 1995-05-04 1995-05-04 반도체 소자의 금속배선 형성방법

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KR100395907B1 (ko) * 2001-05-17 2003-08-27 주식회사 하이닉스반도체 반도체소자의 배선 형성방법

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