KR960032621A - 낮은 면저항을 갖는 접합(Junction) 형성방법 - Google Patents

낮은 면저항을 갖는 접합(Junction) 형성방법 Download PDF

Info

Publication number
KR960032621A
KR960032621A KR1019950003738A KR19950003738A KR960032621A KR 960032621 A KR960032621 A KR 960032621A KR 1019950003738 A KR1019950003738 A KR 1019950003738A KR 19950003738 A KR19950003738 A KR 19950003738A KR 960032621 A KR960032621 A KR 960032621A
Authority
KR
South Korea
Prior art keywords
junction
amorphous silicon
silicon layer
ions
metal ions
Prior art date
Application number
KR1019950003738A
Other languages
English (en)
Other versions
KR0144020B1 (ko
Inventor
이길호
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950003738A priority Critical patent/KR0144020B1/ko
Priority to US08/604,909 priority patent/US5677213A/en
Priority to CN96101496A priority patent/CN1077723C/zh
Priority to TW085102097A priority patent/TW369683B/zh
Publication of KR960032621A publication Critical patent/KR960032621A/ko
Application granted granted Critical
Publication of KR0144020B1 publication Critical patent/KR0144020B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 낮은 면저항을 갖는 접합 형성방법에 있어서, 반도체기판(1) 중 접합을 형성할 부위의 상부에 비정질 실리콘층(2)을 형성하는 제1단계; 상기 비정질 실리콘층(2)이 형성된 부위에 소정 불순물 이온(3)을 주입하는 제2단계; 상기 비정질 실리콘층이 형성된 부위에 소정 금속 이온(4)을 주입하는 제3단계; 및 상기 불순물 및 금속 이온이 주입된 반도체기판(1)을 열처리하는 제4단계를 포함하는 것을 특징으로 하여, 접합의 소모없이 얕은 두께의 실리사이드층(6)을 형성할 수 있어 낮은 면저항과 보다 얕은 접합을 동시에 충족시키고, 이에 따라 소자의 집적도 및 속도를 향상시키는 특유의 효과가 있는 접합 형성방법에 관한것이다.

Description

낮은 면저항을 갖는 접합(Junction) 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 내지 제1D도는 본 발명에 따른 MOS 트랜지스터의 형성 공정도.

Claims (6)

  1. 낮은 면저항을 갖는 접합 형성방법에 있어서, 반도체기판 중 접합을 형성할 부위의 상부에 비정질 실리콘층을 형성하는 제1단계; 상기 비정질 실리콘층이 형성된 부위에 소정 불순물 이온을 주입하는 제2단계; 상기 비정질 실리콘층이 형성된 부위에 소정 금속 이온을 주입하는 제3단계; 및 상기 불순물 및 금속 이온이 주입된 반도체기판을 열처리하는 제4단계를 포함하는 것을 특징으로 하는 접합 형성방법.
  2. 제1항에 있어서, 상기 제2단계는, 상기 불순물은 BF2이온인 것을 특징으로 하는 접합 형성방법.
  3. 제1항 또는 제3항에 있어서, 상기 제2단계는, 상기 불순물 이온의 투사범위(projected range)를 상기 비정질 실리콘층의 중앙에 설정하는 것을 특징으로 하는 접합 형성방법.
  4. 제1항에 있어서, 상기 제3단계에서 금속 이온은, 텅스텐 이온인 것을 특징으로 하는 접합 형성방법.
  5. 제1항 또는 제4항에 있어서, 상기 제3단계는, 상기 금속 이온의 주입 에너지를 적어도 상기 제2단계의 불순물 이온주입시의 주입 에너지보다 낮게 설정하는 것을 특징으로 하는 접합 형성방법.
  6. 제5항에 있어서, 상기 제3단계는, 상기 금속 이온의 투사범위(projected range)를 상기 비정질 실리콘층의 중앙에 설정하는 것을 특징으로 하는 접합 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950003738A 1995-02-24 1995-02-24 낮은 면저항을 갖는 접합 형성방법 KR0144020B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950003738A KR0144020B1 (ko) 1995-02-24 1995-02-24 낮은 면저항을 갖는 접합 형성방법
US08/604,909 US5677213A (en) 1995-02-24 1996-02-22 Method for forming a semiconductor device having a shallow junction and a low sheet resistance
CN96101496A CN1077723C (zh) 1995-02-24 1996-02-24 在mosfet的硅衬底上形成低薄层电阻结的方法
TW085102097A TW369683B (en) 1995-02-24 1996-02-24 A method for forming a semiconductor device having a shallow junction and a low sheet resistance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950003738A KR0144020B1 (ko) 1995-02-24 1995-02-24 낮은 면저항을 갖는 접합 형성방법

Publications (2)

Publication Number Publication Date
KR960032621A true KR960032621A (ko) 1996-09-17
KR0144020B1 KR0144020B1 (ko) 1998-08-17

Family

ID=19408780

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950003738A KR0144020B1 (ko) 1995-02-24 1995-02-24 낮은 면저항을 갖는 접합 형성방법

Country Status (4)

Country Link
US (1) US5677213A (ko)
KR (1) KR0144020B1 (ko)
CN (1) CN1077723C (ko)
TW (1) TW369683B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100505405B1 (ko) * 1999-06-23 2005-08-05 주식회사 하이닉스반도체 반도체 소자의 게이트 전극 형성방법

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100202633B1 (ko) * 1995-07-26 1999-06-15 구본준 반도체 소자 제조방법
TW320752B (en) * 1996-11-18 1997-11-21 United Microelectronics Corp Metal gate electrode process
US5891791A (en) * 1997-05-27 1999-04-06 Micron Technology, Inc. Contamination free source for shallow low energy junction implants
KR100268871B1 (ko) * 1997-09-26 2000-10-16 김영환 반도체소자의제조방법
US6025242A (en) * 1999-01-25 2000-02-15 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation
US5998248A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region
US5998273A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions
US6022771A (en) * 1999-01-25 2000-02-08 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions
KR100313510B1 (ko) * 1999-04-02 2001-11-07 김영환 반도체 소자의 제조방법
US6534402B1 (en) * 2001-11-01 2003-03-18 Winbond Electronics Corp. Method of fabricating self-aligned silicide
KR100475086B1 (ko) * 2002-08-09 2005-03-10 삼성전자주식회사 스플릿 게이트 sonos eeprom 및 그 제조방법
US7271443B2 (en) * 2004-08-25 2007-09-18 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method for the same
WO2007105157A2 (en) * 2006-03-14 2007-09-20 Nxp B.V. Source and drain formation
CN102074465B (zh) * 2009-11-24 2012-04-18 上海华虹Nec电子有限公司 一种双阱制造工艺方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208829A (ja) * 1985-03-14 1986-09-17 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP2868796B2 (ja) * 1989-09-19 1999-03-10 富士通株式会社 半導体装置の製造方法
JPH0415917A (ja) * 1990-05-09 1992-01-21 Nec Corp シャロウジャンクションの形成方法
KR100209856B1 (ko) * 1990-08-31 1999-07-15 가나이 쓰도무 반도체장치의 제조방법
JPH04354328A (ja) * 1991-05-31 1992-12-08 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
JP3285934B2 (ja) * 1991-07-16 2002-05-27 株式会社東芝 半導体装置の製造方法
JPH06163576A (ja) * 1992-11-20 1994-06-10 Nippon Steel Corp 半導体装置の製造方法
US5393687A (en) * 1993-12-16 1995-02-28 Taiwan Semiconductor Manufacturing Company Method of making buried contact module with multiple poly si layers
US5439831A (en) * 1994-03-09 1995-08-08 Siemens Aktiengesellschaft Low junction leakage MOSFETs
US5536676A (en) * 1995-04-03 1996-07-16 National Science Council Low temperature formation of silicided shallow junctions by ion implantation into thin silicon films
US5585295A (en) * 1996-03-29 1996-12-17 Vanguard International Semiconductor Corporation Method for forming inverse-T gate lightly-doped drain (ITLDD) device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100505405B1 (ko) * 1999-06-23 2005-08-05 주식회사 하이닉스반도체 반도체 소자의 게이트 전극 형성방법

Also Published As

Publication number Publication date
TW369683B (en) 1999-09-11
US5677213A (en) 1997-10-14
CN1077723C (zh) 2002-01-09
CN1138748A (zh) 1996-12-25
KR0144020B1 (ko) 1998-08-17

Similar Documents

Publication Publication Date Title
KR960032621A (ko) 낮은 면저항을 갖는 접합(Junction) 형성방법
KR920017245A (ko) 반도체장치와 그의 제조방법
KR970053884A (ko) Mos 트랜지스터를 독립적으로 형성할 수 있는 반도체 집적 회로 디바이스를 제조하기 위한 방법
WO1998053491A3 (en) Manufacture of a semiconductor device with a mos transistor having an ldd structure
KR970053886A (ko) 씨모오스(cmos) 소자 제조방법
EP0794563A3 (en) Semiconductor device having oxygen-doped silicon layer so as to restrict diffusion from heavily doped silicon layer and process of fabrication thereof
KR940004711A (ko) 폴리실리콘층 형성방법
KR920020594A (ko) Ldd 트랜지스터의 구조 및 제조방법
KR960026179A (ko) 반도체 소자의 콘택구조 및 콘택형성방법
KR950030381A (ko) 다결정실리콘 소오스, 드레인(source, drain)을 갖는 상보형 트랜지스터 및 그 제조방법
KR970054171A (ko) 액세스(Access) 트랜지스터에 대한 드라이브(Driver) 트랜지스터의 셀 비율 증대 방법
KR940016931A (ko) 확산원과 실리사이드 형성을 위한 비정질 실리콘을 접합에 이용하는 트랜지스터 제조방법
KR950021743A (ko) 반도체 소자의 모스펫 제조방법
KR910010714A (ko) 메모리 집적회로 및 그 제조공정
KR960026217A (ko) 반도체 소자 제조방법
KR920022555A (ko) 반도체 장치의 제조방법
KR970003406A (ko) 반도체장치의 제조방법
KR970030317A (ko) 반도체소자 제조 방법
KR970003690A (ko) 초고집적화용 낮은 접합 형성방법
KR950015569A (ko) 반도체장치의 제조방법
KR950012645A (ko) 반도체 장치의 박막 트랜지스터 제조방법
KR970054354A (ko) 바이폴라 접합 트랜지스터 및 그 제조방법
KR920015424A (ko) 반도체 제조 방법
KR920017241A (ko) 바이-모스 에스램 셀의 제조방법
KR970003912A (ko) 바이 씨 모스(BiCMOS) 장치 및 그 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130426

Year of fee payment: 16

FPAY Annual fee payment

Payment date: 20140324

Year of fee payment: 17

EXPY Expiration of term