CN1077723C - 在mosfet的硅衬底上形成低薄层电阻结的方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 23
- 150000002500 ions Chemical class 0.000 claims abstract description 14
- 229910001428 transition metal ion Inorganic materials 0.000 claims abstract description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052723 transition metal Inorganic materials 0.000 claims 1
- 150000003624 transition metals Chemical class 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 4
- -1 boron ion Chemical class 0.000 description 18
- 229910052796 boron Inorganic materials 0.000 description 13
- 229910021341 titanium silicide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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Abstract
本发明提供一种在硅衬底上形成低薄层电阻结的方法,该方法包括以下步骤:在所说硅衬底上形成非晶硅层;将杂质离子注入所说非晶硅层;将过渡金属离子注入所说非晶硅层;热处理所说非晶硅层和硅衬底,使过渡金属离于扩散到所说硅衬底的表面,使所说杂质离子扩散到所说硅衬底里。
Description
本发明涉及形成具有浅结和低薄层电阻的半导体器件的方法,尤其涉及制造能防止结击穿和结漏电流增加的在MOSFET的硅衬底上形成低薄层电阻结的方法。
通常,MOS晶体管结形成于硅衬底和诸如源/漏区这样的有源区之间。
在常规MOSFET中,一般用硅化钛层来形成具有低薄层电阻的器件。在给硅衬底注入杂质离子后,通过第一热处理在那里形成结。接着在离子注入区形成钛层,并且通过第二热处理形成硅化钛层。
然而,在进行第二热处理时,掺杂进衬底的杂质离子又重新扩散到硅化钛层,之后硅化钛层和硅衬底间界面上的杂质浓度急据减小,从而生成了肖特基结。这样,就产生了一些象结击穿电压降低和结漏电流增加之类的问题。
此外,因为随半导体器件集成度变高,结的深度变浅,致使薄层电阻增加给发展高速度器件造成了更大困难。
本发明的一个目的是提供一种没有硅层消耗形成同时具有浅结和低薄层电阻的半导体器件的方法。
本发明的一个方面是,提供一种在硅衬底上形成低薄层电阻的结的方法,该方法包括以下步骤:在硅衬底上形成包括一栅极区、一源极区和一漏极区的MOSFET;在源/漏极区上形成一非晶硅层;将杂质离子注入所说非晶硅层;将过渡金属离子注入所说非晶硅层;热处理所说非晶硅层和硅衬底,从而使所说过渡金属离子扩散到所说硅衬底的表面和使所说杂质离子扩散进硅衬底。
从下面参照附图对实施例的描述可明显看出本发明的其它目的和方面。
图1A至1D是表示根据本发明的一个实施例形成MOSFET的方法的横截面图。
参照图1A至1D,下面对本发明的实施例进行详细描述。
首先,如图1A所示,在硅衬底1上由栅氧化层10,栅极11和侧壁氧化层12构成一个通用的MOSFET,这些是所属技术领域的普通技术人员所熟知的。在形成侧壁氧化层12之前,可以将杂质离子注入进硅衬底1来形成LDD(轻掺杂漏)结构,离子注入是用栅极11上的侧壁氧化层12和一绝缘层(未示出)作离子注入阻挡层。在形成源/漏区的暴露的硅衬底上淀积厚度为“T”即200-300的非晶硅层13。
接下来,如图1B所示,通过将BF2离子注入非晶硅层13,使硼离子14定位。当硼离子14注入进硅衬底1时,就会因为硼离子的小尺寸而发生严重的硼离子14的沟道作用。因此,要在硼离子14注入进硅衬底1的情况下形成浅结是很困难的。再看图1A,非晶硅层13对浅结的影响是利用沟道作用来防止硼离子14渗入硅衬底1。而且必须控制加速硼离子14的能量,以免它们渗入硅衬底1和非晶硅层13的界面。在一个优选实施例中,硼离子14的射入范围设置在非晶硅层13的一半厚处,即,硼离子14的射入深度为0.5T。
如图1C所示,为了在不消耗硅衬底1的情况下形成薄硅化物层,必须以小于硼离子14注入的能量将钨离子15注入进非晶硅层13。当然,像钛或钴这样的过渡金属离子可以代替钨离子15。特别是,必须控制钨离子15的能量才能使之不注入硅衬底1。在优选实施例中,钨离子15的射入范围设置在非晶硅层13的一半厚度处。
最后,如图1D所示,在将硼和钨离子15注入到非晶硅层13后,对晶片施行迅速热处理,使在非晶硅层13中的钨和硼离子15和14向硅衬底1扩散。由于硼离子14的扩散系数比钨离子15的高,就使源/漏区16在硅衬底1里形成,在源/漏区上面形成了硅化钨层17。
从上面的描述可以明显看出,本发明具有能通过形成具有低薄层电阻的浅结改进器件速度的很好效果。
尽管以上参照本发明所公开的优选实施例阐明了发明目的,但本领域技术人员很清楚,任何不脱离本发明权利要求书所公开的本发明的精神和范围的修正、增加和替代都是可能的。
Claims (5)
1、一种在MOSFET的硅衬底上形成低薄层电阻结的方法,
其特征在于,该方法包括以下步骤:
在硅衬底上形成包括一栅极区、一源极区和一漏极区的MOSFET;
在源/漏极区上形成一非晶硅层;
将杂质离子注入所说非晶硅层;
将过渡金属离子注入所说非晶硅层;和
热处理所说非晶硅层和硅衬底,使所说过渡金属离子扩散到所说硅衬底的表面,使所说杂质离子扩散进所说硅衬底。
2、根据权利要求1的方法,其特征在于,所说杂质离子为BF2离子。
3、根据权利要求1的方法,其特征在于,所说杂质离子的射入范围被设置在所说非晶硅层的半厚度处。
4、根据权利要求1的方法,其特征在于,所说过渡金属是钨、钛或钴之一。
5、根据权利要求1的方法,其特征在于,所说过渡金属离子的射入范围被设置在所说非晶硅层的半厚度处。
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KR3738/1995 | 1995-02-24 | ||
KR3738/95 | 1995-02-24 | ||
KR1019950003738A KR0144020B1 (ko) | 1995-02-24 | 1995-02-24 | 낮은 면저항을 갖는 접합 형성방법 |
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CN1138748A CN1138748A (zh) | 1996-12-25 |
CN1077723C true CN1077723C (zh) | 2002-01-09 |
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CN96101496A Expired - Fee Related CN1077723C (zh) | 1995-02-24 | 1996-02-24 | 在mosfet的硅衬底上形成低薄层电阻结的方法 |
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Country | Link |
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US (1) | US5677213A (zh) |
KR (1) | KR0144020B1 (zh) |
CN (1) | CN1077723C (zh) |
TW (1) | TW369683B (zh) |
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KR100202633B1 (ko) * | 1995-07-26 | 1999-06-15 | 구본준 | 반도체 소자 제조방법 |
TW320752B (en) * | 1996-11-18 | 1997-11-21 | United Microelectronics Corp | Metal gate electrode process |
US5891791A (en) * | 1997-05-27 | 1999-04-06 | Micron Technology, Inc. | Contamination free source for shallow low energy junction implants |
KR100268871B1 (ko) * | 1997-09-26 | 2000-10-16 | 김영환 | 반도체소자의제조방법 |
US6022771A (en) * | 1999-01-25 | 2000-02-08 | International Business Machines Corporation | Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions |
US5998248A (en) * | 1999-01-25 | 1999-12-07 | International Business Machines Corporation | Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region |
US6025242A (en) * | 1999-01-25 | 2000-02-15 | International Business Machines Corporation | Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation |
US5998273A (en) * | 1999-01-25 | 1999-12-07 | International Business Machines Corporation | Fabrication of semiconductor device having shallow junctions |
KR100313510B1 (ko) * | 1999-04-02 | 2001-11-07 | 김영환 | 반도체 소자의 제조방법 |
KR100505405B1 (ko) * | 1999-06-23 | 2005-08-05 | 주식회사 하이닉스반도체 | 반도체 소자의 게이트 전극 형성방법 |
US6534402B1 (en) * | 2001-11-01 | 2003-03-18 | Winbond Electronics Corp. | Method of fabricating self-aligned silicide |
KR100475086B1 (ko) * | 2002-08-09 | 2005-03-10 | 삼성전자주식회사 | 스플릿 게이트 sonos eeprom 및 그 제조방법 |
US7271443B2 (en) * | 2004-08-25 | 2007-09-18 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method for the same |
WO2007105157A2 (en) * | 2006-03-14 | 2007-09-20 | Nxp B.V. | Source and drain formation |
CN102074465B (zh) * | 2009-11-24 | 2012-04-18 | 上海华虹Nec电子有限公司 | 一种双阱制造工艺方法 |
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JPH04354328A (ja) * | 1991-05-31 | 1992-12-08 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置の製造方法 |
EP0526043A1 (en) * | 1991-07-16 | 1993-02-03 | Kabushiki Kaisha Toshiba | Semiconductor device with low resistance contact and method of manufacturing the same |
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JPS61208829A (ja) * | 1985-03-14 | 1986-09-17 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2868796B2 (ja) * | 1989-09-19 | 1999-03-10 | 富士通株式会社 | 半導体装置の製造方法 |
JPH0415917A (ja) * | 1990-05-09 | 1992-01-21 | Nec Corp | シャロウジャンクションの形成方法 |
KR100209856B1 (ko) * | 1990-08-31 | 1999-07-15 | 가나이 쓰도무 | 반도체장치의 제조방법 |
JPH06163576A (ja) * | 1992-11-20 | 1994-06-10 | Nippon Steel Corp | 半導体装置の製造方法 |
US5393687A (en) * | 1993-12-16 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Method of making buried contact module with multiple poly si layers |
US5439831A (en) * | 1994-03-09 | 1995-08-08 | Siemens Aktiengesellschaft | Low junction leakage MOSFETs |
US5536676A (en) * | 1995-04-03 | 1996-07-16 | National Science Council | Low temperature formation of silicided shallow junctions by ion implantation into thin silicon films |
US5585295A (en) * | 1996-03-29 | 1996-12-17 | Vanguard International Semiconductor Corporation | Method for forming inverse-T gate lightly-doped drain (ITLDD) device |
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1995
- 1995-02-24 KR KR1019950003738A patent/KR0144020B1/ko not_active IP Right Cessation
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1996
- 1996-02-22 US US08/604,909 patent/US5677213A/en not_active Expired - Lifetime
- 1996-02-24 CN CN96101496A patent/CN1077723C/zh not_active Expired - Fee Related
- 1996-02-24 TW TW085102097A patent/TW369683B/zh not_active IP Right Cessation
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH04354328A (ja) * | 1991-05-31 | 1992-12-08 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置の製造方法 |
EP0526043A1 (en) * | 1991-07-16 | 1993-02-03 | Kabushiki Kaisha Toshiba | Semiconductor device with low resistance contact and method of manufacturing the same |
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CN1138748A (zh) | 1996-12-25 |
TW369683B (en) | 1999-09-11 |
US5677213A (en) | 1997-10-14 |
KR0144020B1 (ko) | 1998-08-17 |
KR960032621A (ko) | 1996-09-17 |
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