KR960019785A - Mos형 반도체 장치 - Google Patents

Mos형 반도체 장치 Download PDF

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KR960019785A
KR960019785A KR1019950041831A KR19950041831A KR960019785A KR 960019785 A KR960019785 A KR 960019785A KR 1019950041831 A KR1019950041831 A KR 1019950041831A KR 19950041831 A KR19950041831 A KR 19950041831A KR 960019785 A KR960019785 A KR 960019785A
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cell structure
channel region
semiconductor device
mos
region
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다츠히코 후지히라
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나카자토 요시히코
후지덴키 가부시키가이샤
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Abstract

본 발명은 제1도전형의 반도체 기판의 표면층에 사각형의 제2도전형 채널 영역, 그 중앙부에 고불순물 농도의 웰 영역, 표면층에 제1도전형 소스 영역, 표면상의 MOS구조를 구비한 FET의 셀 구조의 채널 영역의 각부로의 애벌런치 전류의 집중을 막고, 내압, 애벌런치 내량을 향상시킨다.
셀 구조의 사각형의 채널 영역 한변과 인접하는 채널 영역의 한변이 연결되도록 배치한다. 예컨대 장발형의 채널 영역의 단변끼리를 연결함으로써, 채널 영역의 각과 같이 돌출한 부분이 없어지고, 각부로의 애벌런치 전류의 집중이 없어지기 때문에 애벌런치 내량이 향상된다. 또한, 공핍층의 곡률이 작아지고, 내압이 향상된다. 채널 영역의 연결부는 불순물의 횡방향 확산으로 형성하고, 연결부상에는 가는 다결정 실리콘을 남겨서 인접하는 셀 구조의 게이트 전극을 접속한다.

Description

MOS형 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예의 MOSFET의 상부 구조를 제외한 평면도,
제2(a)도는 제1실시예의 MOSFET의 제1도의 A-A선 단면도,
제2(b)도는 제1도의 B-B선 단면도,
제3도는 제1도의 MOSFET의 주변부의 단면도.

Claims (15)

  1. 제1도전형 반도체층의 표면층에 형성된 제2도전형 채널 영역과, 그 채널 영역의 표면층에 형성된 제1도전형 소스 영역과의 적어도 두개의 변이 평행하게 형성되는 네개의 주변(主邊)을 가진 사각형의 셀 구조의 복수개를 구비한 MOS형 반도체 장치에 있어서, 하나의 사각형의 셀 구조의 채널 영역의 한 변이 인접하는 셀 구조의 채널 영역의 한변과 연결되어 있는 것을 특징으로 하는 MOS형 반도체 장치.
  2. 제1항에 있어서, 하나의 셀 구조가 장방형이고, 그 채널 영역의 단변이 인접하는 셀 구조의 채널 영역의 한변과 연결되어 있는 것을 특징으로 하는 MOS형 반도체 장치.
  3. 제2항에 있어서, 하나의 사각형의 셀 구조의 채널 영역의 단변이 인접하는 셀 구조의 채널 영역의 단변과 연결되어 있는 것을 특징으로 하는 MOS형 반도체 장치.
  4. 제3항에 있어서, 두개의 셀 구조의 채널 영역의 단변끼리가 연결된 부분의 측방에 별도의 셀 구조의 채널 영역의 한변이 연결되어 있는 것을 특징으로 하는 MOS형 반도체 장치.
  5. 제1항 내지 제4항중 어느 한 항에 있어서, 반도체칩의 셀 구조를 배열한 부분의 최외주부에 셀 구조의 채널 영역의 외측의 변의 일부가 반도체칩의 변과 평행한 외주 셀 구조를 설치한 것을 특징으로 하는 MOS형 반도체 장치.
  6. 제5항에 있어서, 외주 셀 구조가 셀 구조의 칩 중앙에 가까운 부분에만 제1도전형 소스 영역을 갖는 것을 특징으로 하는 MOS형 반도체 장치.
  7. 제5항에 있어서, 외주 셀 구조가 내측의 셀 구조보다 면적이 넓은 것을 특징으로 하는 MOS형 반도체 장치.
  8. 제1항 내지 제4항중 어느 한 항에 있어서, 반도체칩의 셀 구조를 배열한 부분의 최외주부의 각부에 채널 영역의 외측의 변이 반도체칩의 각을 향하는 원호형인 외각 셀 구조를 설치한 것을 특징으로 하는 MOS형 반도체 장치.
  9. 제8항에 있어서, 외각 셀 구조가 다른 외주 셀 구조보다 면적이 넓은 것을 특징으로 하는 MOS형 반도체 장치.
  10. 제1항 내지 제4항중 어느 한 항에 있어서, 반도체칩의 셀 구조를 배열한 부분의 최외주부의 각부에 셀 구조의 채널 영역의 외측의 변이 반도체칩의 각을 향하는 원호를 본뜬 절선형인 외각 셀 구조를 설치한 것을 특징으로 하는 MOS형 반도체 장치.
  11. 제10항에 있어서, 외각 셀 구조가 다른 외주 셀 구조보다 면적이 넓은 것을 특징으로 하는 MOS형 반도체 장치.
  12. 제1항 내지 제4항중 어느 한 항에 있어서, 제2도전형 채널 영역의 표면층의 일부에 채널 영역보다 불순물 농도가 높고, 확산 깊이가 얕은 제2도전형의 얕은 베이스 영역을 갖는 것을 특징으로 하는 MOS형 반도체 장치.
  13. 제12항에 있어서, 얕은 베이스 영역의 아래쪽에 제2도전형의 영역으로서 채널 영역만을 갖는 것을 특징으로 하는 MOS형 반도체 장치.
  14. 제1항 내지 제4항중 어느 한 항에 있어서, 연결된 채널 영역상에 게이트 전극을 갖는 것을 특징으로 하는 MOS형 반도체 장치.
  15. 제1항 내지 제4항중 어느 한 항에 있어서, 채널 영역의 연결부가 불순물의 횡방향 확산층으로 이루어진 것을 특징으로 하는 MOS형 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950041831A 1994-11-21 1995-11-17 Mos형반도체장치 KR100321355B1 (ko)

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GB9713375D0 (en) * 1997-06-26 1997-08-27 Zetex Plc Power fet device
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KR100321355B1 (ko) 2002-08-22
TW280945B (ko) 1996-07-11
DE69530871D1 (de) 2003-06-26
DE69507933T2 (de) 1999-08-19
EP0717449A2 (en) 1996-06-19
EP1284507A3 (en) 2005-05-18
EP0717449B1 (en) 1999-02-24
EP0849805B1 (en) 2003-05-21
DE69507933D1 (de) 1999-04-01
EP0717449A3 (ko) 1996-07-03
EP0849805A1 (en) 1998-06-24
EP1284507A2 (en) 2003-02-19
DE69530871T2 (de) 2004-03-11

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