KR950034834A - 모스(mos)형 반도체 장치 - Google Patents

모스(mos)형 반도체 장치 Download PDF

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KR950034834A
KR950034834A KR1019950000201A KR19950000201A KR950034834A KR 950034834 A KR950034834 A KR 950034834A KR 1019950000201 A KR1019950000201 A KR 1019950000201A KR 19950000201 A KR19950000201 A KR 19950000201A KR 950034834 A KR950034834 A KR 950034834A
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semiconductor device
mos
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channel region
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다츠히코 후지히라
다케요시 니시무라
다카시 고바야시
도시히로 아라이
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나카자토 요시히코
후지 덴키 가부시키가이샤
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Abstract

본 발명의 목적은 제1도전형의 반도체 기판의 표면층에 방형의 제2도전형 채널 영역과, 그 중앙부에 고불순물 농도의 웰 영역과, 표면층에 제1도전형 소스영역과, 표면상의 MOS 구조를 구비하는 FET의 셀구조의 채널영역의 각부에의 애벌런치 전류의 집중을 방지하고, 내압, 애벌런치 내량을 향상시키는데 있다.
근접하는 셀구조의 채널 영역의 각간의 거리가 변간의 거리보다 작아지도록, 특히 대각선이 일직선상에 있도록 셀구조를 배치함으로써 채널영역의 각부가 근접해서 공핍층이 핀치오프하기 쉬워지므로 각부에의 애벌런치 전류의 집중이 작아진다. 또한 각부간을 고 저항률의 조형상 영역으로 연결함으로써 공핍층의 확산을 용이하게 하는 것도 효과적이다.

Description

모스(MOS)형 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예의 MOSFET의 상부 구조를 제거한 평면도.

Claims (18)

  1. 제1도전형의 반도체층의 표면층의 제2도전형의 채널 영역과, 그 채널 영역의 표면층의 제1도전형의 소스영역이 각변을 서로 평행으로 하여 형성되는 4개의 주변을 갖는 방형의 셀구조의 복수개를 구비하는 것에 있어서, 서로 각을 마주보고 대향하는 2개의 셀구조의 채널 영역의 각간의 거리가 서로 변을 마주보고 대향하는 2개의 셀구조의 채널 영역의 변간의 거리보다 작은 것을 특징으로 하는 MOS형 반도체 장치.
  2. 제1항에 있어서, 가장 근접되는 2개의 셀구조의 대각선이 일직선상에 있도록 셀구조가 배치되는 것을 특징으로 하는 MOS형 반도체 장치.
  3. 제1항에 있어서, 가장 근접되는 2개의 셀구조의 대각에 있어서, 채널 영역의 간격이 4㎛이하인 것을 특징으로 하는 MOS형 반도체 장치.
  4. 제1항에 있어서, 가장 근접되는 2개의 셀구조의 대각에 있어서, 채널 영역끼리가 연결되는 것을 특징으로 하는 MOS형 반도체 장치.
  5. 제1항 내지 제3항중 어느 한 항에 있어서, 2개의 근접 셀구조의 채널 영역간의 채널 영역의 각을 연결하는 일직선상에서 제1도전형의 반도체층의 표면층에 채널 영역보다 얕고, 채널 영역보다 고 저항률의 제2도전형의 조형상 영역이 채널 영역에 연결해서 형성되는 것을 특징으로 하는 MOS형 반도체 장치.
  6. 제1항 내지 제3항 중 어느 한 항에 있어서, 2개의 근접 셀구조의 채널 영역간의 채널 영역의 각을 연결하는 일직선상에서 제1도전형의 반도체층의 표면층에 채널 영역보다 얕고, 제1도전형의 반도체층보다 고 저항률의 제1도전형의 조형상 영역이 채널 영역에 인접해서 형성되는 것을 특징으로 하는 MOS형 반도체 장치.
  7. 제5항에 있어서, 조형상 영역에 연결하여 채널 영역내에 제2도전형보다 불순물 농도가 높은 영역이 형성되는 것을 특징으로 하는 MOS형 반도체 장치.
  8. 제6항에 있어서, 조형상 영역에 연결하여 채널 영역내에 제2도전형보다 불순물 농도가 높은 영역이 형성되는 것을 특징으로 하는 MOS형 반도체 장치.
  9. 제1항, 제2항, 제3항, 제4항, 제7항 또는 제8항에 있어서, 반도체 칩의 셀구조를 정렬한 부분의 최오주부에 셀구조의 채널 영역의 외측의 변의 일부가 반도체 칩의 변과 평행을 이루는 외주 셀구조를 설치하는 것을 특징으로 하는 MOS형 반도체 장치.
  10. 제9항에 있어서, 외주 셀구조가 셀구조의 칩의 중앙에 근접한 부분에만 제1도전형 소스 영역을 갖는 것을 특징으로 하는 MOS형 반도체 장치.
  11. 제9항에 있어서, 외주 셀구조가 내측의 셀구조보다 면적이 넓은 것을 특징으로 하는 MOS형 반도체 장치.
  12. 제1항, 제2항, 제3항, 제4항, 제7항, 제8항, 제10항 또는 제11항에 있어서, 반도체 칩의 셀구조를 정렬한 부분의 최외주부의 각부에 채널 영역의 외측의 변이 반도체 칩의 각에 대향하는 원호상을 이루는 외각 셀구조를 설치한 것을 특징으로 하는 MOS형 반도체 장치.
  13. 제1항, 제2항, 제3항, 제4항, 제7항, 제8항, 제10항 또는 제11항에 있어서, 반도체 칩의 셀구조를 정렬한 부분의 최외주부의 각부에 셀구조의 채널 영역의 외측의 변이 반도체 칩의 각에 대향하는 원호를 모방한 절선형상인 외각 셀구조를 설치한 것을 특징으로 하는 MOS형 반도체 장치.
  14. 제12항에 있어서, 외각 셀구조가 다른외주 셀구조보다 면적이 넓은 것을 특징으로 하는 MOS형 반도체 장치.
  15. 제13항에 있어서, 외각 셀구조가 다른 외주 셀구조보다 면적이 넓은 것을 특징으로 하는 MOS형 반도체 장치.
  16. 제1항, 제2항, 제3항, 제4항, 제7항, 제8항, 제10항, 제11항, 제14항 또는 제15항에 있어서, 제2도전형 채널 영역의 표면층의 일부에 채널 영역보다 불순물 농도가 높고, 확산 깊이가 얕은 제2도전형의 얕은 베이스 영역을 갖는 것을 특징으로 하는 MOS형 반도체 장치.
  17. 제16항에 있어서, 얕은 베이스 영역의 하방에 제2도전형의 영역으로서 채널 영역만을 갖는 것을 특징으로 하는 MOS형 반도체 장치.
  18. 제1도전형의 반도체층의 표면층의 제2도전형의 채널 영역과, 그 채널 영역의 표면층의 제1도전형의 소스 영역이 각 변을 서로 평행으로 해서 형성되는 4개의 주변을 갖는 방형의 셀구조의 복수개를 구비하고, 상기 제1도전형의 반도체층의 표면 근방에 제1도전형 반도체층 보다 저 저항률의 제1도전형 반도체 영역을 구비한 것에 있어서, 서로 각을 마주보고 대향하는 2개의 셀구조의 채널 영역의 각간의 거리가 서로 변을 마주보고 대향하는 2개의 셀구조의 채널 영역의 변간이 거리보다 작은 것을 특징으로 하는 MOS형 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950000201A 1994-01-07 1995-01-07 모스(mos)형 반도체 장치 KR950034834A (ko)

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TW280945B (ko) 1994-11-21 1996-07-11 Fuji Electric Co Ltd
TW344130B (en) 1995-10-11 1998-11-01 Int Rectifier Corp Termination structure for semiconductor device and process for its manufacture
US5940721A (en) * 1995-10-11 1999-08-17 International Rectifier Corporation Termination structure for semiconductor devices and process for manufacture thereof
DE19606983C2 (de) * 1996-02-24 2000-01-20 Semikron Elektronik Gmbh Leistungshalbleiterbauelement mit planarem Aufbau
GB9713375D0 (en) * 1997-06-26 1997-08-27 Zetex Plc Power fet device
GB9726829D0 (en) * 1997-12-19 1998-02-18 Philips Electronics Nv Power semiconductor devices
WO1999052150A1 (en) * 1998-04-03 1999-10-14 Zetex Plc Guard structure for bipolar semiconductor device
US6022790A (en) * 1998-08-05 2000-02-08 International Rectifier Corporation Semiconductor process integration of a guard ring structure
GB2373634B (en) 2000-10-31 2004-12-08 Fuji Electric Co Ltd Semiconductor device
WO2003028108A1 (fr) * 2001-09-19 2003-04-03 Kabushiki Kaisha Toshiba Semi-conducteur et procede de fabrication
US9214572B2 (en) 2013-09-20 2015-12-15 Monolith Semiconductor Inc. High voltage MOSFET devices and methods of making the devices
US9991376B2 (en) 2013-09-20 2018-06-05 Monolith Semiconductor Inc. High voltage MOSFET devices and methods of making the devices
CN111725318B (zh) * 2020-06-18 2024-04-09 湖南国芯半导体科技有限公司 一种功率半导体器件的元胞结构及其制作方法
CN114420745B (zh) * 2022-03-30 2022-06-28 深圳芯能半导体技术有限公司 一种碳化硅mosfet及其制备方法
CN114744049B (zh) * 2022-06-13 2022-09-27 瑞能半导体科技股份有限公司 碳化硅mosfet半导体器件及制作方法
CN115548101B (zh) * 2022-11-25 2023-03-10 浙江大学 一种碳化硅mosfet晶体管器件

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