DE19540665A1 - Halbleiterbauelement und Verfahren zu dessen Herstellung - Google Patents

Halbleiterbauelement und Verfahren zu dessen Herstellung

Info

Publication number
DE19540665A1
DE19540665A1 DE19540665A DE19540665A DE19540665A1 DE 19540665 A1 DE19540665 A1 DE 19540665A1 DE 19540665 A DE19540665 A DE 19540665A DE 19540665 A DE19540665 A DE 19540665A DE 19540665 A1 DE19540665 A1 DE 19540665A1
Authority
DE
Germany
Prior art keywords
concentration
aligned
self
semiconductor device
switching element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19540665A
Other languages
English (en)
Other versions
DE19540665C2 (de
Inventor
Nobuyuki Kasai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE19540665A1 publication Critical patent/DE19540665A1/de
Application granted granted Critical
Publication of DE19540665C2 publication Critical patent/DE19540665C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0891—Source or drain regions of field-effect devices of field-effect transistors with Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8128—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with recessed gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
DE19540665A 1994-11-01 1995-10-31 Halbleiterbauelement und Verfahren zu dessen Herstellung Expired - Fee Related DE19540665C2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP26859294 1994-11-01
JP14873195A JP3651964B2 (ja) 1994-11-01 1995-06-15 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE19540665A1 true DE19540665A1 (de) 1996-06-13
DE19540665C2 DE19540665C2 (de) 2002-08-08

Family

ID=26478837

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19540665A Expired - Fee Related DE19540665C2 (de) 1994-11-01 1995-10-31 Halbleiterbauelement und Verfahren zu dessen Herstellung

Country Status (3)

Country Link
US (1) US5648668A (de)
JP (1) JP3651964B2 (de)
DE (1) DE19540665C2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1117036A (ja) * 1997-06-26 1999-01-22 Sharp Corp 半導体記憶装置の製造方法
JPH11354541A (ja) * 1998-06-11 1999-12-24 Fujitsu Quantum Devices Kk 半導体装置およびその製造方法
US6171918B1 (en) 1998-06-22 2001-01-09 International Business Machines Corporation Depleted poly mosfet structure and method
US6103607A (en) * 1998-09-15 2000-08-15 Lucent Technologies Manufacture of MOSFET devices
US5998848A (en) * 1998-09-18 1999-12-07 International Business Machines Corporation Depleted poly-silicon edged MOSFET structure and method
US6436749B1 (en) 2000-09-08 2002-08-20 International Business Machines Corporation Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion
JP4540347B2 (ja) * 2004-01-05 2010-09-08 シャープ株式会社 窒化物半導体レーザ素子及び、その製造方法
US7157297B2 (en) * 2004-05-10 2007-01-02 Sharp Kabushiki Kaisha Method for fabrication of semiconductor device
JP4651312B2 (ja) * 2004-06-10 2011-03-16 シャープ株式会社 半導体素子の製造方法
US7812408B1 (en) 2007-10-16 2010-10-12 Altera Corporation Integrated circuits with metal-oxide-semiconductor transistors having enhanced gate depletion layers
US8232603B2 (en) * 2009-03-19 2012-07-31 International Business Machines Corporation Gated diode structure and method including relaxed liner
US10211005B2 (en) 2016-11-21 2019-02-19 Schneider Electric USA, Inc. Cost reduced synchronized-switching contactor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4792531A (en) * 1987-10-05 1988-12-20 Menlo Industries, Inc. Self-aligned gate process
JP2727590B2 (ja) * 1988-10-13 1998-03-11 日本電気株式会社 Ｍｉｓ型半導体装置
JPH03191532A (ja) * 1989-12-20 1991-08-21 Nec Corp ショットキー障壁接合ゲート型電界効果トランジスタ
KR100254005B1 (ko) * 1991-08-02 2000-04-15 가나이 쓰도무 반도체 장치 및 그 제조 방법
JP3075831B2 (ja) * 1991-08-20 2000-08-14 三洋電機株式会社 電界効果型トランジスタ及びその製造方法
JPH05267346A (ja) * 1992-03-18 1993-10-15 Sumitomo Electric Ind Ltd 電界効果トランジスタおよびその製造方法

Also Published As

Publication number Publication date
JPH08186130A (ja) 1996-07-16
DE19540665C2 (de) 2002-08-08
JP3651964B2 (ja) 2005-05-25
US5648668A (en) 1997-07-15

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee