KR960019531A - 폴리실리콘 패턴 형성방법 - Google Patents

폴리실리콘 패턴 형성방법 Download PDF

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Publication number
KR960019531A
KR960019531A KR1019940029782A KR19940029782A KR960019531A KR 960019531 A KR960019531 A KR 960019531A KR 1019940029782 A KR1019940029782 A KR 1019940029782A KR 19940029782 A KR19940029782 A KR 19940029782A KR 960019531 A KR960019531 A KR 960019531A
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South Korea
Prior art keywords
polysilicon
etching
gas
film
florin
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KR1019940029782A
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English (en)
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KR0151618B1 (ko
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이계남
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문정환
금성일렉트론 주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

본 발명은 의한 폴리실리콘 패턴 형성방법은 기판상에 표면보호막과 졀연층을 형성시킨 다음 기판전면에 폴리실리콘막을 형성시키는 단계와, 폴리실리콘막상에 포토레지스트로 식각시킬 부위를 정의하는 단계와, 포토레지스트를 마스크로하여 상기 폴리실리콘막을 HBr가스를 포함하는 가스분위기속에서 선택적으로 1차 식각시키는 단계와, 폴리실리콘막의 1차 식각후에 잔재하는 폴리실리콘 잔류물을 플로린기(F*)나 플로린-카본(C-F*)기 가스를 포함하는 가스분위기속에서 2차 식각시키는 단계를 포함하여 이루어진다.

Description

폴리실리콘 패턴 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 폴리실리콘 패턴 형성방법의 공정단계를 도시한 도면.

Claims (4)

  1. 반도체 기판상에 형성된 폴리실리콘막을 식각하여 폴리실리콘 패턴을 형성시키는 방법에 있어서, 1) 기판상에 표면보호막과 졀연층을 형성시킨 다음 기판전면에 폴리실리콘막을 형성시키는 단계와, 2) 상기 폴리실리콘막상에 포토레지스트로 식각시킬 부위를 정의하는 단계와, 3) 상기 포토레지스트를 마스크로하여 상기 폴리실리콘막을 HBr가스를 포함하는 가스분위기속에서 선택적으로 1차 식각시키는 단계와, 4) 상기 폴리실리콘막의 1차 식가후에 잔재하는 폴리실리콘 잔류물을 소정 가스를 포함하는 가스분위기속에서 2차 식각시키는 단계를 포함하여 이루어진 폴리실리콘 패턴 형성방법.
  2. 제1항에 있어서, 상기 4)단계에서 상기 폴리실리콘막 식각후에 잔재하는 폴리실리콘 잔류물을 플로린기(F*)나 플로린-카본(C-F*)기 가스를 포함하는 가스분위기속에서 2차 식각시키는 것이 특징인 폴리실리콘 패턴 형성방법.
  3. 제2항에 있어서, 상기 폴리실리콘 잔류물을 식각시킬때에 폴리실리콘 잔류물의 식각률이 분당 1500Å (1분) 이하이고, 폴리실리콘 잔류물과 표면보호막 두께의 최소 식각선택비는 2:1이하의 조건으로 폴리실리콘 잔류물을 식각시키는 것을 특징으로 하는 폴리실리콘 패턴 형성방법.
  4. 제2항에 있어서, 상기 플로린(F*)기나 플로린-카본(C-F*)기 가스를 포함하는 가스분위기로 CF4, F2F6, SF6등의 가스를 사용하는 것이 특징인 폴리실리콘 패턴 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940029782A 1994-11-14 1994-11-14 폴리실리콘 패턴 형성방법 KR0151618B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940029782A KR0151618B1 (ko) 1994-11-14 1994-11-14 폴리실리콘 패턴 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940029782A KR0151618B1 (ko) 1994-11-14 1994-11-14 폴리실리콘 패턴 형성방법

Publications (2)

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KR960019531A true KR960019531A (ko) 1996-06-17
KR0151618B1 KR0151618B1 (ko) 1998-12-01

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KR1019940029782A KR0151618B1 (ko) 1994-11-14 1994-11-14 폴리실리콘 패턴 형성방법

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