KR960016662A - 2층 및 다층 인쇄 회로 기판의 쓰루-홀 도금 방법 - Google Patents

2층 및 다층 인쇄 회로 기판의 쓰루-홀 도금 방법 Download PDF

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Publication number
KR960016662A
KR960016662A KR1019950034835A KR19950034835A KR960016662A KR 960016662 A KR960016662 A KR 960016662A KR 1019950034835 A KR1019950034835 A KR 1019950034835A KR 19950034835 A KR19950034835 A KR 19950034835A KR 960016662 A KR960016662 A KR 960016662A
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South Korea
Prior art keywords
acid
polythiophene
process according
layer
printed circuit
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KR1019950034835A
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English (en)
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KR100294040B1 (ko
Inventor
볼프 게르하르트-디터
요나스 프리드리히
쇼맥커 라인하르트
Original Assignee
크누트 샤우에르테 · 클라우스 로이터
바이엘 악티엔게젤샤프트
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Publication of KR960016662A publication Critical patent/KR960016662A/ko
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Publication of KR100294040B1 publication Critical patent/KR100294040B1/ko

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H05K3/424—Plated through-holes or plated via connections characterised by electroplating method by direct electroplating
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/54—Electroplating of non-metallic surfaces
    • C25D5/56—Electroplating of non-metallic surfaces of plastics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/032—Materials
    • H05K2201/0329—Intrinsically conductive polymer [ICP]; Semiconductive polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0779—Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
    • H05K2203/0786—Using an aqueous solution, e.g. for cleaning or during drilling of holes
    • H05K2203/0796—Oxidant in aqueous solution, e.g. permanganate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

본 발명은 하기 일반식 (I)의 단량체 티오펜의 마이크로에멀젼을 사용하여 도전성 폴리티오펜층을 형성하고, 이어서 또는 동시에 산으로 처리하여 폴리티오펜의 도전층을 쓰루-홀의 격벽 위에 생성시키고, 마지막으로 금속을 상기 도전성 기재 위에 전착시키는 것을 특징으로 하는, 쓰루-홀의 격벽 위에 폴리티오펜의 도전층을 도포하고 쓰루-홀의 격벽 위에 구리를 전착시킴으로써 인쇄 회로 기판을 쓰루-홀 도금시키는 방법에 관한 것이다.
식 중, X는 산소 또는 단일 결합이고, R1및 R2는 서로 독립적으로 수소 또는 C1-C4알킬기이거나, 또는 함께 임의 치환된 C1-C4알킬렌 잔기 또는 1,2-시클로헥실렌 잔기를 형성한다.

Description

2층 및 다층 인쇄 회로 기판의 쓰루-홀 도금 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (11)

  1. 하기 일반식 (I)의 단량체 티오펜의 마이크로에멀젼을 사용하여 도전성 포리티오펜층을 형성하고, 이어서 또는 동시에 산으로 처리하여 폴리티오펜의 도전층을 쓰루-홀(through-hole)의 격벽 위에 생성시키고, 마지막으로 금속을 상기 도전성 기재 위에 전착시키는 것을 특징으로 하는, 쓰루-홀의 격벽 위에 폴리티오펜의 도전층을 도포하고 쓰루-홀의 격벽 위에 구리를 전착시킴으로써 인쇄 회로 기판을 쓰루-홀 도금시키는 방법.
    식 중, X는 산소 또는 단일 결합이고, R1및 R2는 서로 독립적으로 수소 또는 C1-C4알킬기이거나, 또는 함께 임의 치환된 C1-C4알킬렌 잔기 또는 1,2-시클로헥실렌 잔기를 형성한다.
  2. 제1항에 있어서, a)구리 적층된 다층 기판(기재)에 쓰루-홀을 제조하고, b) 쓰루-홀을 예비 산화 처리하고, c) 물로 세척하고, d) 일반식(I)의 티오펜의 마이크로에멀젼으로 처리하고, e) 산으로 처리하고, f)물로 세척하고, g) 구리를 전착시키는 단계를 포함하는 방법.
  3. 제2항에 있어서, 예비 산화 처리 b)가 알칼리 금속 과망산염으로 수행하여 이산화망간층을 형성하는 것을 특징으로 하는 방법.
  4. 제1항 또는 제2항에 있어서, 일반식(I)의 티오펜으로서 3,4-에틸렌디옥시티오펜을 사용하는 것을 특징으로 하는 방법.
  5. 제2항에 있어서, 산 e)로서 중합체 포리술폰산을 사용하는 것을 특징으로 하는 방법.
  6. 제2항에 있어서, 산 e)로서 중합체와 혼합된 수성 무기 강산을 사용하는 것을 특징으로 하는 방법.
  7. 제2항에 있어서, 산 e)로서 최소 농도가 10%인 무기 강산 수용액을 사용하는 것을 특징으로 하는 방법.
  8. 제2항에 있어서, 산 e)로서 15 내지 20%의 황산을 사용하는 것을 특징으로 하는 방법.
  9. 제2항에 있어서, 산 e)로서 30 내지 50%의 인산을 사용하는 것을 특징으로 하는 방법.
  10. 제2항에 있어서, 단계 d) 및 e)를 한 단계로 합한 것을 특징으로 하는 방법.
  11. 제1항 내지 제10항에 따라 제조된 다층 인쇄 회로 기판.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950034835A 1994-10-12 1995-10-11 2층및다층인쇄회로판의관통-홀도금방법_ KR100294040B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP4436391.5 1994-10-12
DE4436391A DE4436391A1 (de) 1994-10-12 1994-10-12 Verfahren zur direkten galvanischen Durchkontaktierung von zweilagigen Leiterplatten und Multilayern

Publications (2)

Publication Number Publication Date
KR960016662A true KR960016662A (ko) 1996-05-22
KR100294040B1 KR100294040B1 (ko) 2001-09-17

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Country Status (5)

Country Link
US (1) US5575898A (ko)
EP (1) EP0707440B1 (ko)
JP (1) JP2733461B2 (ko)
KR (1) KR100294040B1 (ko)
DE (2) DE4436391A1 (ko)

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DE59509934D1 (de) 2002-01-24
DE4436391A1 (de) 1996-04-18
JP2733461B2 (ja) 1998-03-30
JPH08213753A (ja) 1996-08-20
EP0707440A1 (de) 1996-04-17
US5575898A (en) 1996-11-19
KR100294040B1 (ko) 2001-09-17
EP0707440B1 (de) 2001-12-12

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