KR960015215A - 에지 트리거 래치를 갖춘 레벨 센서티브 래치를 에뮬레이션하는 시뮬레이션 방법 및 장치 - Google Patents

에지 트리거 래치를 갖춘 레벨 센서티브 래치를 에뮬레이션하는 시뮬레이션 방법 및 장치 Download PDF

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Publication number
KR960015215A
KR960015215A KR1019950035520A KR19950035520A KR960015215A KR 960015215 A KR960015215 A KR 960015215A KR 1019950035520 A KR1019950035520 A KR 1019950035520A KR 19950035520 A KR19950035520 A KR 19950035520A KR 960015215 A KR960015215 A KR 960015215A
Authority
KR
South Korea
Prior art keywords
clock signal
frequency
high frequency
signal
system clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019950035520A
Other languages
English (en)
Korean (ko)
Inventor
디. 맥민 브라이언
가나파시 고피
Original Assignee
미키오 이시마루
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미키오 이시마루, 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 미키오 이시마루
Publication of KR960015215A publication Critical patent/KR960015215A/ko
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
KR1019950035520A 1994-10-17 1995-10-14 에지 트리거 래치를 갖춘 레벨 센서티브 래치를 에뮬레이션하는 시뮬레이션 방법 및 장치 Withdrawn KR960015215A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/323,644 US5721695A (en) 1994-10-17 1994-10-17 Simulation by emulating level sensitive latches with edge trigger latches
US08/323,644 1994-10-17

Publications (1)

Publication Number Publication Date
KR960015215A true KR960015215A (ko) 1996-05-22

Family

ID=23260088

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950035520A Withdrawn KR960015215A (ko) 1994-10-17 1995-10-14 에지 트리거 래치를 갖춘 레벨 센서티브 래치를 에뮬레이션하는 시뮬레이션 방법 및 장치

Country Status (4)

Country Link
US (1) US5721695A (https=)
EP (1) EP0712208A2 (https=)
JP (1) JPH08254571A (https=)
KR (1) KR960015215A (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6028993A (en) * 1997-01-10 2000-02-22 Lucent Technologies Inc. Timed circuit simulation in hardware using FPGAs
US6338158B1 (en) * 1997-10-31 2002-01-08 Vlsi Technology, Inc. Custom IC hardware modeling using standard ICs for use in IC design validation
US6618698B1 (en) 1999-08-12 2003-09-09 Quickturn Design Systems, Inc. Clustered processors in an emulation engine
KR20020078818A (ko) * 2001-04-10 2002-10-19 삼성전자 주식회사 마이크로 컴퓨터 개발 시스템에 내장된 에뮬레이터
US7260515B2 (en) * 2001-08-20 2007-08-21 Sun Microsystems, Inc. Method and apparatus for simulating transparent latches
US8645117B2 (en) * 2010-05-27 2014-02-04 Freescale Semiconductor, Inc. Clock simulation device and methods thereof
KR101731929B1 (ko) * 2011-02-08 2017-05-02 삼성전자주식회사 재구성 가능 프로세서 및 구동 제어 방법

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US4435763A (en) * 1981-04-13 1984-03-06 Texas Instruments Incorporated Multiprogrammable input/output circuitry
DE3376592D1 (en) * 1982-07-13 1988-06-16 Nec Corp Logic simulator operable on level basis and on logic block basis on each level
US4807115A (en) * 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
FR2554952B1 (fr) * 1983-11-15 1989-04-28 Telecommunications Sa Procede et systeme d'adressage pour memoire dynamique
JPH0658631B2 (ja) * 1983-12-19 1994-08-03 株式会社日立製作所 デ−タ処理装置
US4627085A (en) * 1984-06-29 1986-12-02 Applied Micro Circuits Corporation Flip-flop control circuit
US4697241A (en) * 1985-03-01 1987-09-29 Simulog, Inc. Hardware logic simulator
US4937827A (en) * 1985-03-01 1990-06-26 Mentor Graphics Corporation Circuit verification accessory
JPS61229133A (ja) * 1985-04-03 1986-10-13 Nec Corp シングルチツプマイクロコンピユ−タ用エミユレ−タ
JPH0743733B2 (ja) * 1985-12-11 1995-05-15 株式会社日立製作所 論理シミュレーション方法
US4937770A (en) * 1986-02-07 1990-06-26 Teradyne, Inc. Simulation system
US4744084A (en) * 1986-02-27 1988-05-10 Mentor Graphics Corporation Hardware modeling system and method for simulating portions of electrical circuits
US5133062A (en) * 1986-03-06 1992-07-21 Advanced Micro Devices, Inc. RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory
US4939637A (en) * 1988-02-10 1990-07-03 Metalink Corporation Circuitry for producing emulation mode in single chip microcomputer
US4864161A (en) * 1988-05-05 1989-09-05 Altera Corporation Multifunction flip-flop-type circuit
JPH02133834A (ja) * 1988-11-14 1990-05-23 Nec Corp インサートキットエミュレータ
US5050195A (en) * 1989-02-23 1991-09-17 Northern Telecom Limited Narrow range digital clock circuit
US5226126A (en) * 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5027355A (en) * 1989-04-14 1991-06-25 Control Data Corporation Logic circuit and design method for improved testability
US5095454A (en) * 1989-05-25 1992-03-10 Gateway Design Automation Corporation Method and apparatus for verifying timing during simulation of digital circuits
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US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
EP0445454B1 (en) * 1990-03-08 1997-06-18 International Business Machines Corporation Hardware simulator
US5059818A (en) * 1990-06-01 1991-10-22 Advanced Micro Devices, Inc. Self-regulating clock generator
US5140180A (en) * 1990-08-24 1992-08-18 Ncr Corporation High speed cmos flip-flop employing clocked tristate inverters
US5438672A (en) * 1990-12-18 1995-08-01 National Semiconductor Corporation Microcontroller emulator for plural device architecture configured by mode control data and operated under control code transmitted via same switching bus
US5321828A (en) * 1991-06-07 1994-06-14 Step Engineering High speed microcomputer in-circuit emulator
JP2927108B2 (ja) * 1992-07-22 1999-07-28 日本電気株式会社 インサーキットエミュレータ
US5425036A (en) * 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
GB2273835B (en) * 1992-12-22 1996-08-14 Advanced Risc Mach Ltd Bistable circuit

Also Published As

Publication number Publication date
EP0712208A3 (https=) 1996-06-12
EP0712208A2 (en) 1996-05-15
JPH08254571A (ja) 1996-10-01
US5721695A (en) 1998-02-24

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951014

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid