KR960009248B1 - Clock-synchronous semiconductor memory device and the access method thereof - Google Patents

Clock-synchronous semiconductor memory device and the access method thereof Download PDF

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Publication number
KR960009248B1
KR960009248B1 KR93004252A KR930004252A KR960009248B1 KR 960009248 B1 KR960009248 B1 KR 960009248B1 KR 93004252 A KR93004252 A KR 93004252A KR 930004252 A KR930004252 A KR 930004252A KR 960009248 B1 KR960009248 B1 KR 960009248B1
Authority
KR
South Korea
Prior art keywords
clock
memory device
semiconductor memory
access method
synchronous semiconductor
Prior art date
Application number
KR93004252A
Other languages
English (en)
Other versions
KR930020279A (ko
Inventor
Haruki Toda
Hitoshi Kuyama
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of KR930020279A publication Critical patent/KR930020279A/ko
Application granted granted Critical
Publication of KR960009248B1 publication Critical patent/KR960009248B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
KR93004252A 1992-03-19 1993-03-19 Clock-synchronous semiconductor memory device and the access method thereof KR960009248B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP92-063844 1992-03-19
JP6384492 1992-03-19

Publications (2)

Publication Number Publication Date
KR930020279A KR930020279A (ko) 1993-10-19
KR960009248B1 true KR960009248B1 (en) 1996-07-16

Family

ID=13241051

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93004252A KR960009248B1 (en) 1992-03-19 1993-03-19 Clock-synchronous semiconductor memory device and the access method thereof

Country Status (4)

Country Link
US (3) US5818793A (ko)
EP (1) EP0561370B1 (ko)
KR (1) KR960009248B1 (ko)
DE (1) DE69325119T2 (ko)

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US6624679B2 (en) 2000-01-31 2003-09-23 Stmicroelectronics S.R.L. Stabilized delay circuit
EP1122733A1 (en) 2000-01-31 2001-08-08 STMicroelectronics S.r.l. Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit
EP1122887A1 (en) 2000-01-31 2001-08-08 STMicroelectronics S.r.l. Pre-charging circuit of an output buffer
EP1122737A1 (en) 2000-01-31 2001-08-08 STMicroelectronics S.r.l. Circuit for managing the transfer of data streams from a plurality of sources within a system
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JP4741122B2 (ja) * 2001-09-07 2011-08-03 富士通セミコンダクター株式会社 半導体装置及びデータ転送方法
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EP0561370B1 (en) * 1992-03-19 1999-06-02 Kabushiki Kaisha Toshiba A clock-synchronous semiconductor memory device and access method thereof
JP2740097B2 (ja) * 1992-03-19 1998-04-15 株式会社東芝 クロック同期型半導体記憶装置およびそのアクセス方法
JP2830594B2 (ja) * 1992-03-26 1998-12-02 日本電気株式会社 半導体メモリ装置

Also Published As

Publication number Publication date
DE69325119T2 (de) 1999-11-04
DE69325119D1 (de) 1999-07-08
US5818793A (en) 1998-10-06
EP0561370A2 (en) 1993-09-22
EP0561370B1 (en) 1999-06-02
US5986968A (en) 1999-11-16
KR930020279A (ko) 1993-10-19
US5798979A (en) 1998-08-25
EP0561370A3 (ko) 1994-12-21

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