KR960006541A - 고속동작 제어 시스템 - Google Patents

고속동작 제어 시스템 Download PDF

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Publication number
KR960006541A
KR960006541A KR1019950022825A KR19950022825A KR960006541A KR 960006541 A KR960006541 A KR 960006541A KR 1019950022825 A KR1019950022825 A KR 1019950022825A KR 19950022825 A KR19950022825 A KR 19950022825A KR 960006541 A KR960006541 A KR 960006541A
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KR
South Korea
Prior art keywords
capacitor
pll
integrating
integrating capacitor
current
Prior art date
Application number
KR1019950022825A
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English (en)
Other versions
KR100371421B1 (ko
Inventor
마크 뱃저 데이빗
Original Assignee
구니유키 아키야마
톰슨 콘슈머 일렉트로닉스, 인코오포레이티드
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Application filed by 구니유키 아키야마, 톰슨 콘슈머 일렉트로닉스, 인코오포레이티드 filed Critical 구니유키 아키야마
Publication of KR960006541A publication Critical patent/KR960006541A/ko
Application granted granted Critical
Publication of KR100371421B1 publication Critical patent/KR100371421B1/ko

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/44Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PLL의 적분 커패시터(18)의 더 급속한 충전은 더 큰 주파수 변화가 요구되는 경우에 제공된다. 일실시예에서, 위상 고정 루프(PLL)회로(10)는 적분 커패시터(18)를 충전 또는 방전시키기 위해 전류를 차단 또는 공급한다. 커패시터를 통과하는 전류에 비례하는 임계 전압은 PLL이 고정될때까지 외부 전원(+Vcc,-Vcc)으로 부터의 적분 커패시터(18)에 적절한 극성의 더 많은 전류를 공급 또는 차단하는 회로를 턴온시킨다. PLL이 고정된 경우, PLL에 의해 약간의 보정 전류가 요구된다면, 약간의 보정 전류는 증가 회로(Q1,Q2,20,36)를 동작시키기 위해 필요한 임계값 이하가 되며, PLL 루프는 증가 회로(Q1,Q2,20,36)가 제공되지 않은 경우처럼 동작한다. 다른 실시예에서, 적분 커패시터(18)는 감소된 전체 커패시턴스가 더 신속하게 충전될 수 있도록 적분 커패시터(18)에 직렬로 커패시터(40)를 스위칭가능하게 접속시킴으로서 값이 감소된다.

Description

고속동작 제어 시스템
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도 및 제6도는 일부는 블록도로 회로도로 도시된 본 발명의 실시예에 대한 도면.

Claims (2)

  1. 에러를 나타내는 신호를 제공하는 수단(34)과; 에러를 나타내는 상기 신호에 응답하여 에러를 보정하며, 제1응답 시간을 갖는 에러 표시 신호를 적분하는 적분 커패시터(18)를 포함하는 에러 보정수단을 구비한 제어 시스템에 있어서, 적분 커패시터(18)에 제2커패시터(40)를 직렬 접속시키므로써 제1응답시간에서 제2응답시간까지의 에러를 나타내는 신호를 적분하는 적분 커패시터(18)에 대한 응답시간을 감소시키는 수단(40,42)을 포함하는 것을 특징으로 하는 제어시스템.
  2. 신호 선택에 응답하여 수신기의 동조를 위한 동조 신호를 제공하며, 제1응답 시간을 갖는 동조 신호를 적분하기 위한 적분 커패시터(18)를 포함하는 수단(34)을 구비한 신호 수신기용 동조 시스템에 있어서, 적분 커패시터(18)에 제2커패시터(40)를 직렬 접속시키므로써 제1응답시간에서 제2응답시간까지의 에러를 나타내는 신호를 적분하는 적분 커패시터(18)에 대한 응답시간을 감소시키는 수단(40,42)을 포함하는 것을 특징으로 하는 동조 시스템.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950022825A 1994-07-28 1995-07-28 고속동작제어시스템 KR100371421B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9415185A GB9415185D0 (en) 1994-07-28 1994-07-28 Fast acting control system
GB9415185.9 1994-07-28

Publications (2)

Publication Number Publication Date
KR960006541A true KR960006541A (ko) 1996-02-23
KR100371421B1 KR100371421B1 (ko) 2003-03-31

Family

ID=10758986

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1019950022824A KR100387015B1 (ko) 1994-07-28 1995-07-28 제어시스템및동조시스템
KR1019950022825A KR100371421B1 (ko) 1994-07-28 1995-07-28 고속동작제어시스템

Family Applications Before (1)

Application Number Title Priority Date Filing Date
KR1019950022824A KR100387015B1 (ko) 1994-07-28 1995-07-28 제어시스템및동조시스템

Country Status (10)

Country Link
US (2) US5764300A (ko)
EP (2) EP0695038A1 (ko)
JP (2) JPH0865154A (ko)
KR (2) KR100387015B1 (ko)
CN (2) CN1088959C (ko)
CA (2) CA2154811C (ko)
DE (1) DE69522621T2 (ko)
GB (1) GB9415185D0 (ko)
MX (1) MX9503264A (ko)
MY (2) MY113396A (ko)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2317279B (en) * 1996-09-11 2001-01-24 Nec Technologies Frequency synthesisers
US5870439A (en) * 1997-06-18 1999-02-09 Lsi Logic Corporation Satellite receiver tuner chip having reduced digital noise interference
US6188739B1 (en) 1997-10-21 2001-02-13 Level One Communications, Inc. Modified third order phase-locked loop
US6064273A (en) * 1998-06-04 2000-05-16 Adc Telecommunications Phase-locked loop having filter with wide and narrow bandwidth modes
US6526112B1 (en) * 1999-06-29 2003-02-25 Agilent Technologies, Inc. System for clock and data recovery for multi-channel parallel data streams
US6784945B2 (en) * 1999-10-01 2004-08-31 Microtune (Texas), L.P. System and method for providing fast acquire time tuning of multiple signals to present multiple simultaneous images
US6959062B1 (en) 2000-01-28 2005-10-25 Micron Technology, Inc. Variable delay line
US6380810B1 (en) * 2000-08-24 2002-04-30 Tektronix, Inc. Reduced lock time for a phase locked loop
DE60041546D1 (de) * 2000-12-28 2009-03-26 Renesas Tech Corp PLL-Schaltung mit reduzierter Einschwingzeit
US6766154B2 (en) * 2001-03-07 2004-07-20 Northrop Grumman Corporation Fast settling fine stepping phase locked loops
US6504409B1 (en) * 2001-04-17 2003-01-07 K-Tek Corporation Controller for generating a periodic signal with an adjustable duty cycle
US6853227B2 (en) * 2001-04-17 2005-02-08 K-Tek Corporation Controller for generating a periodic signal with an adjustable duty cycle
DE10243504A1 (de) * 2002-09-19 2004-04-01 Robert Bosch Gmbh Schaltungsanordnung und Verfahren zum Abstimmen der Oszillationsfrequenz
US7005929B2 (en) * 2003-12-02 2006-02-28 Intel Corporation Loop filter with active capacitor and method for generating a reference
US7587622B2 (en) * 2005-01-11 2009-09-08 Altera Corporation Power management of components having clock processing circuits
US7369002B2 (en) * 2005-07-28 2008-05-06 Zarlink Semiconductor, Inc. Phase locked loop fast lock method
US7782143B2 (en) 2007-03-08 2010-08-24 Integrated Device Technology, Inc. Phase locked loop and delay locked loop with chopper stabilized phase offset
CN107992152A (zh) * 2018-01-31 2018-05-04 国充充电科技江苏股份有限公司 一种提高模拟积分控制环路响应速度的辅助网路电路

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3064215A (en) * 1958-07-01 1962-11-13 Manson Lab Inc Uhf tuned load circuit
US3389346A (en) * 1964-07-20 1968-06-18 James E. Webb Compensating bandwidth switching transients in an amplifier circuit
US3694776A (en) * 1970-12-14 1972-09-26 Motorola Inc Adaptive filter wherein opposite conductivity transistors are operative in response to signals in excess of predetermined amplitude
JPS52124846A (en) * 1976-04-12 1977-10-20 Fujitsu Ltd Filter switch of digital phase synchronous oscillator
US4053933A (en) * 1976-11-02 1977-10-11 Zenith Radio Corporation Adaptive phase locked loop filter for television tuning
GB2040052B (en) * 1978-12-09 1983-01-26 Racal Dana Instr Ltd Edectrical signal processing
US4243918A (en) * 1979-05-29 1981-01-06 Rca Corporation Signal integrator with time constant controlled by differentiating feedback
US4377728A (en) * 1981-03-04 1983-03-22 Motorola Inc. Phase locked loop with improved lock-in
JPS5827438A (ja) * 1981-08-12 1983-02-18 Fujitsu Ltd Pll回路
JPS5916411A (ja) * 1982-07-19 1984-01-27 Toshiba Corp 時定数切換回路
US4890072A (en) * 1988-02-03 1989-12-26 Motorola, Inc. Phase locked loop having a fast lock current reduction and clamping circuit
US4937538A (en) * 1988-04-05 1990-06-26 U.S. Philips Corporation Circuit arrangement for synchronizing an oscillator
US4937536A (en) * 1988-08-19 1990-06-26 Hughes Aircraft Company Fast settling phase lock loop
JP2879763B2 (ja) * 1989-06-27 1999-04-05 ソニー株式会社 Pllのチャージポンプ回路
DE58909454D1 (de) * 1989-07-06 1995-11-02 Itt Ind Gmbh Deutsche Digitale Steuerschaltung für Abstimmsysteme.
JPH03131105A (ja) * 1989-10-16 1991-06-04 Sanden Corp 直流成分を含む変調信号による周波数変調可能な位相同期ループ回路
DE69129946T2 (de) * 1990-05-21 1999-04-15 Nec Corp Phasenregelkreisschaltung
DE4017491C2 (de) * 1990-05-31 2002-05-08 Siemens Ag Abstimmschaltung
JPH0679346B2 (ja) * 1990-11-01 1994-10-05 富士ゼロックス株式会社 積分器及び画像読取装置
DE4104040C2 (de) * 1991-02-09 2002-08-14 Thomson Brandt Gmbh Verfahren zum Abgleich und Betrieb einer Schaltungsanordnung sowie Schaltungsanordnung zur Durchführung des Verfahrens
JP3208736B2 (ja) * 1991-11-08 2001-09-17 ソニー株式会社 Pll回路
FR2689342A1 (fr) * 1992-03-31 1993-10-01 Sgs Thomson Microelectronics Boucle à verrouillage de fréquence.
US5317283A (en) * 1993-06-08 1994-05-31 Nokia Mobile Phones, Ltd. Method to reduce noise in PLL frequency synthesis

Also Published As

Publication number Publication date
CA2154812C (en) 1999-01-26
EP0695039B1 (en) 2001-09-12
MY113396A (en) 2002-02-28
US5686866A (en) 1997-11-11
DE69522621D1 (de) 2001-10-18
CN1088959C (zh) 2002-08-07
US5764300A (en) 1998-06-09
CN1086067C (zh) 2002-06-05
EP0695039A1 (en) 1996-01-31
JPH0865154A (ja) 1996-03-08
GB9415185D0 (en) 1994-09-21
KR960006488A (ko) 1996-02-23
JP3558750B2 (ja) 2004-08-25
CA2154812A1 (en) 1996-01-29
CA2154811C (en) 1999-01-26
KR100387015B1 (ko) 2003-08-14
CN1128460A (zh) 1996-08-07
EP0695038A1 (en) 1996-01-31
MY113754A (en) 2002-05-31
DE69522621T2 (de) 2002-04-18
KR100371421B1 (ko) 2003-03-31
MX9503264A (es) 1997-08-30
JPH0865155A (ja) 1996-03-08
CN1127445A (zh) 1996-07-24
CA2154811A1 (en) 1996-01-29

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