MX9503264A - Sistema de control, de activacion rapida. - Google Patents

Sistema de control, de activacion rapida.

Info

Publication number
MX9503264A
MX9503264A MX9503264A MX9503264A MX9503264A MX 9503264 A MX9503264 A MX 9503264A MX 9503264 A MX9503264 A MX 9503264A MX 9503264 A MX9503264 A MX 9503264A MX 9503264 A MX9503264 A MX 9503264A
Authority
MX
Mexico
Prior art keywords
pll
current
loop
tuning
acting control
Prior art date
Application number
MX9503264A
Other languages
English (en)
Other versions
MXPA95003264A (es
Inventor
David Mark Badger
Original Assignee
Thomson Consumer Electronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Consumer Electronics filed Critical Thomson Consumer Electronics
Publication of MXPA95003264A publication Critical patent/MXPA95003264A/es
Publication of MX9503264A publication Critical patent/MX9503264A/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45—Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

Una carga mucho más rápida de un capacitor integrador (18), de un CEF es proporcionada cuando se desean cambios grandes de frecuencia. En una modalidad, el circuito de enganche de fase (CEF) (10), aporta o disipa corriente a fin de cargar o descargar el capacitor integrador (18). Un voltaje de umbral, proporcional a una corriente a través del capacitor enciende un circuito que disipa o aporta más corriente de la polaridad adecuada al capacitor integrador (18) de una fuente externa (+Vcc, -Vcc), hasta que se logra un enganche del CEF. Una vez que se ha logrado el enganche, si el CEF requiere una pequeña corriente de correccion, la pequeña corriente de correccion está por debajo de un umbral requerido a fin de activar el circuito incrementador, y el circuito del CEF se comporta de la manera usual, como si el circuito incrementador (Q1, Q2, 20, 36) no estuviera presente. En otra modalidad, el capacitor integrador (18) es reducido en valor al conectar de manera conmutable un segundo capacitor (40), en serie con el capacitor integrador (18), de tal manera que la capacitancia total reducida de valor disminuido se puede cargar más rápidamente.
MX9503264A 1994-07-28 1995-07-27 Sistema de control, de activacion rapida. MX9503264A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9415185A GB9415185D0 (en) 1994-07-28 1994-07-28 Fast acting control system
GB9415185.9 1994-07-28

Publications (2)

Publication Number Publication Date
MXPA95003264A MXPA95003264A (es) 1997-08-01
MX9503264A true MX9503264A (es) 1997-08-30

Family

ID=10758986

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9503264A MX9503264A (es) 1994-07-28 1995-07-27 Sistema de control, de activacion rapida.

Country Status (10)

Country Link
US (2) US5686866A (es)
EP (2) EP0695038A1 (es)
JP (2) JP3558750B2 (es)
KR (2) KR100371421B1 (es)
CN (2) CN1088959C (es)
CA (2) CA2154811C (es)
DE (1) DE69522621T2 (es)
GB (1) GB9415185D0 (es)
MX (1) MX9503264A (es)
MY (2) MY113754A (es)

Families Citing this family (18)

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GB2317279B (en) * 1996-09-11 2001-01-24 Nec Technologies Frequency synthesisers
US5870439A (en) * 1997-06-18 1999-02-09 Lsi Logic Corporation Satellite receiver tuner chip having reduced digital noise interference
US6188739B1 (en) 1997-10-21 2001-02-13 Level One Communications, Inc. Modified third order phase-locked loop
US6064273A (en) * 1998-06-04 2000-05-16 Adc Telecommunications Phase-locked loop having filter with wide and narrow bandwidth modes
US6526112B1 (en) * 1999-06-29 2003-02-25 Agilent Technologies, Inc. System for clock and data recovery for multi-channel parallel data streams
US6784945B2 (en) 1999-10-01 2004-08-31 Microtune (Texas), L.P. System and method for providing fast acquire time tuning of multiple signals to present multiple simultaneous images
US6959062B1 (en) 2000-01-28 2005-10-25 Micron Technology, Inc. Variable delay line
US6380810B1 (en) * 2000-08-24 2002-04-30 Tektronix, Inc. Reduced lock time for a phase locked loop
EP1220453B1 (en) * 2000-12-28 2009-02-11 Renesas Technology Corp. PLL circuit with reduced settling time
US6766154B2 (en) * 2001-03-07 2004-07-20 Northrop Grumman Corporation Fast settling fine stepping phase locked loops
US6504409B1 (en) * 2001-04-17 2003-01-07 K-Tek Corporation Controller for generating a periodic signal with an adjustable duty cycle
US6853227B2 (en) * 2001-04-17 2005-02-08 K-Tek Corporation Controller for generating a periodic signal with an adjustable duty cycle
DE10243504A1 (de) * 2002-09-19 2004-04-01 Robert Bosch Gmbh Schaltungsanordnung und Verfahren zum Abstimmen der Oszillationsfrequenz
US7005929B2 (en) * 2003-12-02 2006-02-28 Intel Corporation Loop filter with active capacitor and method for generating a reference
TWI351818B (en) 2005-01-11 2011-11-01 Altera Corp Power management of components having clock proces
US7369002B2 (en) * 2005-07-28 2008-05-06 Zarlink Semiconductor, Inc. Phase locked loop fast lock method
US7782143B2 (en) 2007-03-08 2010-08-24 Integrated Device Technology, Inc. Phase locked loop and delay locked loop with chopper stabilized phase offset
CN107992152B (zh) * 2018-01-31 2024-09-10 国充充电科技江苏股份有限公司 一种提高模拟积分控制环路响应速度的辅助网路电路

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US3064215A (en) * 1958-07-01 1962-11-13 Manson Lab Inc Uhf tuned load circuit
US3389346A (en) * 1964-07-20 1968-06-18 James E. Webb Compensating bandwidth switching transients in an amplifier circuit
US3694776A (en) * 1970-12-14 1972-09-26 Motorola Inc Adaptive filter wherein opposite conductivity transistors are operative in response to signals in excess of predetermined amplitude
JPS52124846A (en) * 1976-04-12 1977-10-20 Fujitsu Ltd Filter switch of digital phase synchronous oscillator
US4053933A (en) * 1976-11-02 1977-10-11 Zenith Radio Corporation Adaptive phase locked loop filter for television tuning
GB2040052B (en) * 1978-12-09 1983-01-26 Racal Dana Instr Ltd Edectrical signal processing
US4243918A (en) * 1979-05-29 1981-01-06 Rca Corporation Signal integrator with time constant controlled by differentiating feedback
US4377728A (en) * 1981-03-04 1983-03-22 Motorola Inc. Phase locked loop with improved lock-in
JPS5827438A (ja) * 1981-08-12 1983-02-18 Fujitsu Ltd Ｐｌｌ回路
JPS5916411A (ja) * 1982-07-19 1984-01-27 Toshiba Corp 時定数切換回路
US4890072A (en) * 1988-02-03 1989-12-26 Motorola, Inc. Phase locked loop having a fast lock current reduction and clamping circuit
US4937538A (en) * 1988-04-05 1990-06-26 U.S. Philips Corporation Circuit arrangement for synchronizing an oscillator
US4937536A (en) * 1988-08-19 1990-06-26 Hughes Aircraft Company Fast settling phase lock loop
JP2879763B2 (ja) * 1989-06-27 1999-04-05 ソニー株式会社 Ｐｌｌのチャージポンプ回路
DE58909454D1 (de) * 1989-07-06 1995-11-02 Itt Ind Gmbh Deutsche Digitale Steuerschaltung für Abstimmsysteme.
JPH03131105A (ja) * 1989-10-16 1991-06-04 Sanden Corp 直流成分を含む変調信号による周波数変調可能な位相同期ループ回路
EP0595787B1 (en) * 1990-05-21 1998-08-05 Nec Corporation Phase-locked loop circuit
DE4017491C2 (de) * 1990-05-31 2002-05-08 Siemens Ag Abstimmschaltung
JPH0679346B2 (ja) * 1990-11-01 1994-10-05 富士ゼロックス株式会社 積分器及び画像読取装置
DE4104040C2 (de) * 1991-02-09 2002-08-14 Thomson Brandt Gmbh Verfahren zum Abgleich und Betrieb einer Schaltungsanordnung sowie Schaltungsanordnung zur Durchführung des Verfahrens
JP3208736B2 (ja) * 1991-11-08 2001-09-17 ソニー株式会社 Ｐｌｌ回路
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US5317283A (en) * 1993-06-08 1994-05-31 Nokia Mobile Phones, Ltd. Method to reduce noise in PLL frequency synthesis

Also Published As

Publication number Publication date
KR960006541A (ko) 1996-02-23
KR960006488A (ko) 1996-02-23
MY113396A (en) 2002-02-28
JPH0865154A (ja) 1996-03-08
CA2154812A1 (en) 1996-01-29
DE69522621D1 (de) 2001-10-18
JPH0865155A (ja) 1996-03-08
DE69522621T2 (de) 2002-04-18
EP0695039B1 (en) 2001-09-12
CA2154811C (en) 1999-01-26
KR100387015B1 (ko) 2003-08-14
EP0695038A1 (en) 1996-01-31
CN1127445A (zh) 1996-07-24
CA2154811A1 (en) 1996-01-29
CA2154812C (en) 1999-01-26
US5764300A (en) 1998-06-09
CN1086067C (zh) 2002-06-05
US5686866A (en) 1997-11-11
CN1128460A (zh) 1996-08-07
MY113754A (en) 2002-05-31
GB9415185D0 (en) 1994-09-21
KR100371421B1 (ko) 2003-03-31
JP3558750B2 (ja) 2004-08-25
CN1088959C (zh) 2002-08-07
EP0695039A1 (en) 1996-01-31

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