KR960002765B1 - 절연체 위에 단결정 반도체 제조방법 - Google Patents
절연체 위에 단결정 반도체 제조방법 Download PDFInfo
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- KR960002765B1 KR960002765B1 KR1019920024967A KR920024967A KR960002765B1 KR 960002765 B1 KR960002765 B1 KR 960002765B1 KR 1019920024967 A KR1019920024967 A KR 1019920024967A KR 920024967 A KR920024967 A KR 920024967A KR 960002765 B1 KR960002765 B1 KR 960002765B1
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- 239000012212 insulator Substances 0.000 title claims abstract description 14
- 239000013078 crystal Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000206 photolithography Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-RNFDNDRNSA-N silicon-32 atom Chemical compound [32Si] XUIMIQQOPSSXEZ-RNFDNDRNSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 4
- 239000007800 oxidant agent Substances 0.000 description 4
- 229910021426 porous silicon Inorganic materials 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76272—Vertical isolation by lateral overgrowth techniques, i.e. ELO techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76289—Lateral isolation by air gap
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/154—Solid phase epitaxy
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Abstract
내용 없음.
Description
제1도는 종래의 절연체 위에 단결정 반도체 제조방법을 설명하기 위한 반도체 일부의 단면도.
제2도는 종래의 절연체 위에 단결정 반도체 제조방법을 설명하기 위한 반도체 일부의 단면도.
본 발명은 절연체 위에 단결정 반도체 제조방법에 관한 것으로, 특히 고속, 고품위 특성을 요하는 반도체 소자 제조에 적합하도록 한 소자와 소자와의 격리 공정중 SOI(Silicon on insulator) 기술을 이용한 절연체 위에서 각각 절연된 단결정 반도체의 활성영역을 제조하는 방법에 관한 것이다.
종래의 절연체 위에 단결정 반도체 제조방법 또는 절연체 위에 반도체 소자 제조방법, 간단히 줄여서 부르는 SOI(Silicon On Insulator) 기술로는, SOS(Silicon On Sapphire), SIMOX(Separation by Implanted Oxygen), FIPOS(Full Insolation by Porous Oxided Silicon) 등의 방법이 있다. 본 발명과 유사한 SOI 기술로 FIPOS 기술을 들 수 있는데, 이 FIPOS 기술의 일예가 제1도에 도시한 바와 같은 순서로 이루어져 있다.
P형 실리콘 기판(10)에 P+ 도핑을 위한 보론이온주입을 실시하고, 확산시켜 P+ 영역(12)를 형성하고(제1도의 a), N-활성 영역(14)을 CVD 방식으로 에피택셜 성장(epitaxial growing)시킨 후(제1도의 b), 활성 영역(14a)을 패터닝한다.
이어서 양극 반응(Anodization)을 실시하여 P+ 영역(12)을 부식(corrosion)시켜서 다공성(porous)의 실리콘영역(12a)으로 만든다(제1도의 c).
그후, 다공성 실리콘영역이 작은구멍(pore)을 통하여 산화제(옥시던트 : Oxidant)가 유입되는 성질을 이용하여 산화(oxidation)시켜서 산화막절연층(14b)으로 만들고, 활성영역(14a)을 보호하며 충분히 활성역역이 산화막절연층(12b)으로 격리되고 절연되게 한다(제1도의 d).이때 활성영역(14a)도 표면 일부가 산화되어 절연층(14b)으로 둘러쌓이게 된다.
이와 같은 종래의 기술에서 많은 공정 단계들과 다공성 실리콘 형성이 일반적인 반도체 제조공정이 아닌 양극반응공정을 사용하므로 웨이퍼오염 및 다공성 실리콘 제조의 조절이 매우 어렵다.
본 발명은 보다 간단한 방법으로 절연체 위에 단결정 반도체의 활성영역을 형성하려는 것이다.
본 발명은 제2도의 (a)에 도시된 것처럼, 일반적인 실리콘기판(20)위에 산화공정을 실시하여 산화막(22)를 형성하고, 후에 비정질(Amorphous) 실리콘으로부터 단결정을 형성시키기위한 에피텍셜 성장의 씨(seed)가 될 부분의 단결정기판위의 산화막을 제거하여 윈도우(24)를 연다. 나머지 산화막부분은 후에 필드(Field)산화공정시 옥시던트가 확산되어 산화되는 통로가 된다.
이어서, 제2도의 (b)에 도시된 것처럼, 비정질시리콘(26)을 CVD(Chemical Vapor Deposition)한다. 이어 일반적인 방식으로 제2도의 (c)에 도시된 것처럼, 일반적인 비정질(Amorphous)실리콘이 실리콘기판의 열린 윈도우로부터 단결정(20)으로 성장되게 한다.
다음으로, 제2도의 (d)에 도시된 것처럼, 실리콘 질화막(28)을 데포지션(deposition)하고, 제2도의 (e)에 도시된 것처럼, 소자들이 형성될 활성영역(30)을 사진식각 공정으로 패터닝한다. 패턴닝할 때 매몰된 산화막(22)가 노출될 때까지 식각한다.
제2도의 (f)에 도시된 것처럼, 2차로 실리콘 질화막을 데포지션하고 에치백하여 활성영역의 측벽에 실리콘 질화막의 스페이스(32)를 만들고, 제2도의 (g)에 도시된 것처럼, 필드산화를 실시한다. 필드산화(Field oxidation)시 초기에 형성하였던 산화막(22)을 통하여 옥시던트(oxidant)가 확산(diffusion)되어 실리콘기판(20)과 활성영역(30)을 연결하는 부분의 실리콘(32)이 산화되어 단절되도록 하여 3차원 SOI 구조의 격리가 완성된다.
그 이후, 필요에 따라 제2도의 (h)에 도시된 것처럼, 실리콘 질화막을 식각하여 절연체위에 인접한 활성영역과는 완전히 격리되고 또한 절연된 활성영역을 형성하여 SOI 구조를 완성한다.
본 발명에서는 쉽게 이해할 수 있도록 설명하기 위하여 P나 N형의 반도체 타입을 예로 들었으나, 반대되는 타입의 반도체를 사용하여도 된다는 것은 물론이고, 산화막이나 질화막 대신 비슷한 성질의 절연막이나 식각 선택성이 있는 재질의 막을 사용하여도 된다.
이러한 본 발명의 방법을 이용하면, 기존의 반도체 제조 공정들을 이용하여 쉽게 SOI 타입의 3차원 격리구조를 실현할 수 있다.
Claims (2)
- 절연체 위에 단결정 반도체의 활성영역을 형성하기위한 방법에 있어서, (1) 일반적인 실리콘기판(20)위에 산화공정을 실시하여 절연막(22)를 형성하고, 비정질실리콘으로부터 단결정을 형성시키기위한 에피텍셜성장의 씨가 될 부분의 단결정기판위의 절연막을 제거하여 윈도우(24)를 열고, (2) 비정질실리콘(26)을 화학기상증착하고, 비정질실리콘의 실리콘기판의 열린 윈도우로부터 단결정(20)으로 성장되게 하고, (3) 실리콘 질화막(28)을 데포지션하고, 소자들이 형성될 활성영역(30)을 사진식각 공정으로 패터닝하고, (4) 2차로 실리콘 질화막을 데포지션하고 에치백하여 활성영역의 측벽에 실리콘 질화막의 스페이스(32)을 만들고, (5) 필드산화공정을 실시하여 초기에 형성하였던 산화막(22)을 통하여 옥시던트가 확산되어 실리콘기판(20)과 활성영역(30)을 연결하는 부분의 실리콘(32)이 산화되어 단절되도록 하는 단계들을 포함하여 이루어지는 절연체 위에 단결정 반도체 제조방법.
- 제1항에 있어서, 상기 제(1)단계의 절연막(22)은 실리콘 산화막인 것이 특징인 절연체 위에 단결정 반도체 제조방법.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920024967A KR960002765B1 (ko) | 1992-12-22 | 1992-12-22 | 절연체 위에 단결정 반도체 제조방법 |
DE4341180A DE4341180B4 (de) | 1992-12-22 | 1993-12-02 | Verfahren zur Isolation einer Halbleiterschicht auf einem Isolator zur Festlegung eines aktiven Gebiets |
JP5304106A JPH06232247A (ja) | 1992-12-22 | 1993-12-03 | 絶縁層上に隔離された半導体層を製造する方法 |
US08/540,422 US5686343A (en) | 1992-12-22 | 1995-10-10 | Process for isolating a semiconductor layer on an insulator |
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KR1019920024967A KR960002765B1 (ko) | 1992-12-22 | 1992-12-22 | 절연체 위에 단결정 반도체 제조방법 |
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KR940016597A KR940016597A (ko) | 1994-07-23 |
KR960002765B1 true KR960002765B1 (ko) | 1996-02-26 |
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US (1) | US5686343A (ko) |
JP (1) | JPH06232247A (ko) |
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JP3308245B2 (ja) * | 1999-08-12 | 2002-07-29 | 住友ゴム工業株式会社 | 空気入りタイヤ |
US6037199A (en) * | 1999-08-16 | 2000-03-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | SOI device for DRAM cells beyond gigabit generation and method for making the same |
US6350659B1 (en) * | 1999-09-01 | 2002-02-26 | Agere Systems Guardian Corp. | Process of making semiconductor device having regions of insulating material formed in a semiconductor substrate |
US6326272B1 (en) | 1999-11-18 | 2001-12-04 | Chartered Semiconductor Manufacturing Ltd. | Method for forming self-aligned elevated transistor |
US6174754B1 (en) | 2000-03-17 | 2001-01-16 | Taiwan Semiconductor Manufacturing Company | Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors |
US6319772B1 (en) * | 2000-10-30 | 2001-11-20 | Chartered Semiconductor Manufacturing Ltd. | Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer |
US7125458B2 (en) | 2003-09-12 | 2006-10-24 | International Business Machines Corporation | Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer |
KR100578821B1 (ko) * | 2004-08-24 | 2006-05-11 | 삼성전자주식회사 | 박막 형성 방법 |
US20090200635A1 (en) * | 2008-02-12 | 2009-08-13 | Viktor Koldiaev | Integrated Circuit Having Electrical Isolation Regions, Mask Technology and Method of Manufacturing Same |
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JPS5721856B2 (en) * | 1977-11-28 | 1982-05-10 | Nippon Telegraph & Telephone | Semiconductor and its manufacture |
US4361600A (en) * | 1981-11-12 | 1982-11-30 | General Electric Company | Method of making integrated circuits |
JPS58132919A (ja) * | 1982-02-03 | 1983-08-08 | Nec Corp | 半導体装置の製造方法 |
JPS6124246A (ja) * | 1984-07-13 | 1986-02-01 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置とその製造方法 |
JPS62245646A (ja) * | 1986-04-18 | 1987-10-26 | Sony Corp | 半導体装置の製造方法 |
NL8800847A (nl) * | 1988-04-05 | 1989-11-01 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een soi-struktuur. |
JPH0324719A (ja) * | 1989-06-22 | 1991-02-01 | Canon Inc | 単結晶膜の形成方法及び結晶物品 |
JPH03125458A (ja) * | 1989-10-11 | 1991-05-28 | Canon Inc | 単結晶領域の形成方法及びそれを用いた結晶物品 |
US5308445A (en) * | 1991-10-23 | 1994-05-03 | Rohm Co., Ltd. | Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate |
JP2752868B2 (ja) * | 1992-10-13 | 1998-05-18 | 三田工業株式会社 | インタフェース有効/無効判定装置 |
-
1992
- 1992-12-22 KR KR1019920024967A patent/KR960002765B1/ko not_active IP Right Cessation
-
1993
- 1993-12-02 DE DE4341180A patent/DE4341180B4/de not_active Expired - Fee Related
- 1993-12-03 JP JP5304106A patent/JPH06232247A/ja active Pending
-
1995
- 1995-10-10 US US08/540,422 patent/US5686343A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR940016597A (ko) | 1994-07-23 |
US5686343A (en) | 1997-11-11 |
DE4341180A1 (de) | 1994-06-23 |
JPH06232247A (ja) | 1994-08-19 |
DE4341180B4 (de) | 2006-07-27 |
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