KR960001885A - 반도체 소자의 콘택 식각방법 - Google Patents

반도체 소자의 콘택 식각방법 Download PDF

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Publication number
KR960001885A
KR960001885A KR1019940014575A KR19940014575A KR960001885A KR 960001885 A KR960001885 A KR 960001885A KR 1019940014575 A KR1019940014575 A KR 1019940014575A KR 19940014575 A KR19940014575 A KR 19940014575A KR 960001885 A KR960001885 A KR 960001885A
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South Korea
Prior art keywords
etching
semiconductor device
gas
contact
fluorine
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KR1019940014575A
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English (en)
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KR0137716B1 (ko
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신기수
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김주용
현대전자산업 주식회사
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Priority to KR1019940014575A priority Critical patent/KR0137716B1/ko
Publication of KR960001885A publication Critical patent/KR960001885A/ko
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Publication of KR0137716B1 publication Critical patent/KR0137716B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 콘택 식각방법에 관한 것으로, 식각하는 가스를 탄소에 대한 불소(Fluorine)의 구성비가 1이하인 가스를 사용하여 콘택식각을 하거나 또는 종래의 사용되고 탄소에 대한 불소의 구성비가 1이상인 가스에 수소를 첨가한 가스를 사용하여 건식식각하여 기판에 대한 선택도(Selectivity)를 증가시키며 콘택홀의 프로파일 기울기(Tapering)를 억제하며 마이크로 로우딩(Micro Loading)영향도 감소시키는 반도체 소자의 콘택 식각 방법에 관한 것이다.

Description

반도체 소자의 콘택 식각방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제2도는 본 발명의 반도체 소자 콘택 식각방법에 따라 산화막을 식각한 상태의 단면도.
제3도는 본 발명의 반도체 소자 콘택 식각방법에 따라 서로 다른 크기의 콘택을 형성한 상태의 단면도.

Claims (3)

  1. 반도체 소자의 콘택 식각방법에 있어서, 산화막 식각시, 탄수(C)에 대한 불소(Fluorine)의 구성비가 1이하인 가스를 사용하여 건식식각함으로써, 콘택 식각시 측벽의 산화막에서는 분해가 잘되고 산화막이 아닌 기판에서는 퇴적이 잘 되어 콘택 프로파일이 수직으로 형성되고 선택도를 증가시키도록 한 것을 특징으로 하는 반도체 소자의 콘택 식각방법.
  2. 제1항에 있어서, 상기 탄소(C)에 대한 불소(Fluorine)의 구성비가 1이상인 가스는 C2H2F2, CH3F인 것을 특징으로 하는 반도체 소자의 콘택 식각방법.
  3. 반도체 소자의 콘택 식각방법에 있어서, 산화막 식각시, 탄소(C)에 대한 불소(Fluorine)의 구성비가 1이상인 가스에 수소와 같은 첨가물을 넣은 가스를 사용하여 건식식각함으로써, 콘택 식각시 측벽의 산화막에서는 분해가 잘되고 산화막이 아닌 기판에서는 퇴적이 잘 되어 콘택 프로파일이 수직으로 형성되고 선택도를 증가시키도록 한 것을 특징으로 하는 반도체 소자의 콘택 식각방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940014575A 1994-06-24 1994-06-24 반도체 소자의 콘텍 식각방법 KR0137716B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940014575A KR0137716B1 (ko) 1994-06-24 1994-06-24 반도체 소자의 콘텍 식각방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940014575A KR0137716B1 (ko) 1994-06-24 1994-06-24 반도체 소자의 콘텍 식각방법

Publications (2)

Publication Number Publication Date
KR960001885A true KR960001885A (ko) 1996-01-26
KR0137716B1 KR0137716B1 (ko) 1998-04-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940014575A KR0137716B1 (ko) 1994-06-24 1994-06-24 반도체 소자의 콘텍 식각방법

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KR0137716B1 (ko) 1998-04-27

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