KR950700676A - 고밀도 도체 네트워크 및 그 제조방법과 제조장치(High density conductive networks and method and apparatus for making same) - Google Patents

고밀도 도체 네트워크 및 그 제조방법과 제조장치(High density conductive networks and method and apparatus for making same)

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KR950700676A
KR950700676A KR1019940702819A KR19940702819A KR950700676A KR 950700676 A KR950700676 A KR 950700676A KR 1019940702819 A KR1019940702819 A KR 1019940702819A KR 19940702819 A KR19940702819 A KR 19940702819A KR 950700676 A KR950700676 A KR 950700676A
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South Korea
Prior art keywords
conductive
sheet
layer
conductor
dielectric material
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KR1019940702819A
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English (en)
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에이. 로버츠 죠셉
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에이. 로버츠 죠셉
로크 리미티드 파트너쉽
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Publication of KR950700676A publication Critical patent/KR950700676A/ko

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/14—Mounting supporting structure in casing or on frame or rack
    • H05K7/1438—Back panels or connecting means therefor; Terminals; Coding means to avoid wrong insertion
    • H05K7/1447—External wirings; Wiring ducts; Laying cables
    • H05K7/1451—External wirings; Wiring ducts; Laying cables with connections between circuit boards or units
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R31/00—Coupling parts supported only by co-operation with counterpart
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/045—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by making a conductive layer having a relief pattern, followed by abrading of the raised portions
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0039—Galvanic coupling of ground layer on printed circuit board [PCB] to conductive casing
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/036—Multilayers with layers of different types
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/0707—Shielding
    • H05K2201/0715—Shielding provided by an outer layer of PCB
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49082—Resistor making
    • Y10T29/49083—Heater type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
    • Y10T29/49217—Contact or terminal manufacturing by assembling plural parts by elastic joining
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
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    • Y10T29/49222—Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10T29/49—Method of mechanical manufacture
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    • Y10T29/49906—Metal deforming with nonmetallic bonding

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

연질 또는 경질의 기판상 네트워크(SCN)는 다른 네트워크에 대응하는 컨덕터(6)와 접속하는 자기 정합성의 컨덕터(14)를 구비한다. 도체 네트워크(10)로부터, 전기적 접속부품 또는 회로로 사용가능한 고밀도 접촉 클러스터를 형성할 수가 있다. 이 도체 네트워크(10)를 제조하기 위한 방법 및 장치에는, 도전성 재료(22)의시트로부터, 한쪽이 도체 네트워크를 한정하고, 다른쪽이 제거 재료인 것의 돌출부(24) 및 홈부(26)를 형성해, 다음에 이 제거 재료를 기계적으로 제거하는 것을 포함한다. 이와 같이 해서 형성된 도체 네트워크는 유전층(12)에 의해서 지지된다.

Description

고밀도 도체 네트워크 및 그 제조방법과 제조장치(High density conductive networks and method and apparatus for making same)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본 발명에 의한 프린트 회로에 접속된 자기 정합성 도체 네트워크(SCN)에 대한 부분축 투상도, 제2도는 제1도의 2-2선에 따라 취해진 절단도, 제3도 및 4도는 제1도의 도체 네트워크를 제조할때의 연속 단계를 도시하는 부분축 투상도, 제5도 및 6도는 각각, 제3도 및 4도의 5-5선 및 6-6선에 따라 취해진 단면도, 제10도 및 11도는 각각 납땜 수납부의 지지에 본 도체 컨덕터를 사용한 예를 나타내는 사시도 및 상면도.

Claims (28)

  1. a)평면 형상의 도전성 시티를 제1면상의 유전 재료를 고착시키는 비평면 형상의 패턴으로 형성하는 단계 및 b) 상기 시트의 제2면으로부터 일부를 제거하여, 전기적으로 절연되거나 상기 유전 재료에 지지된 도전 패스를 형성하는 단계를 포함하는 기관상에 도체 네트워크를 제조하는 방법.
  2. 제1항에 있어서, 상기 유전 재료는, 형성 단계 후에 시트의 제1면에 고착되는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  3. 제1항에 있어서, 상기 형성 단계의 결과, 돌출부 및 홈부가 표면의 양쪽에 형성되는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  4. 제3항에 있어서, 상기 제1면에 유전 재료를 고착시킬때 접착제를 사용하여, 상기 접착제가 유전 제료와 제1면 사이의 간극을 충전하는 작용도 하는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  5. 제2항에 있어서, 상기 형성 단계의 결과, 상기 제1면상에만 높아진 패턴이 형성되고, 또한 제거된 부분에 의해 높아진 패턴으로부터 패스가 형성되는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  6. 제5항에 있어서, 상기 시트는 동, 제1면을 한정하는 비교적 얇은 막의 동층 및 제 2 면을 한정하는 비교적 두꺼운 막의 알루미늄층을 포함하는 적층판과, 2개의 다른 도전성 재료의 층을 포함하는 적층판, 제 1면을 한정하는 비교적 얇은 막의 도전성 금속층 및 제 2 면을 한정하는 비교적 두꺼운 막의 유전층을 포함하는 적층판 및 제1면을 한정하는 도전성 재료의 층과 제2면을 한정하는 유전 재료의 층을 포함하는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  7. 제1항에 있어서, 상기 형성 단계와 유전 제료의 부착은 동시에 실행되는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  8. 제7항에 있어서, 상기 동시에 행하여지는 작업은, 유전 재료를 제1면상에 주조 가공하는 것으로 행하여지고, 이때 주조 압력이 평면 형상의 시트를 비평면 형상의 패턴으로 변형시키는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  9. 제1항에 있어서, 상기 제거 단계는 기계 가공인 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  10. 제6항에 있어서, 상기 평면 형상의 시트는 도전층과 유전층을 포함하는 연질 적층판인 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  11. 제10항에 있어서, 상기 적층판은 매우 유연한 것이기 때문에 부분 진공으로 변형하여 비평면 형상 패턴을 한정하는 상기 방법은 부분 진공을 유전층에 제공하여 적층판을 적절한 윤곽 표면을 향하여 끌어 올리는 것을 포함하며, 상기 적층판을 윤곽 표면으로부터 떼어놓을때(release)평면 형상으로 되돌아 오도록 충분히 유연하게 선택되는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  12. 제10 항에 있어서, 상기 적층판이 매우 유연한 관계로 부분 진동으로 변형하여 비평면 형상 패턴을 한정하는 상기 방법은, 부분 진공을 유전충에 제공하여 적층판을 적절한 윤곽 표면을 향하여 끌어 올리는 것 및 상기 높아진 부분을 제거하고, 또한 상기 적층판을 윤곽 표면으로부터 떼어놓은 후에 평면 형상으로 압력을 가하는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  13. 제12항에 있어서, 상기 높아진 부분은 상기 적층판이 부분 진공에 의해서 윤곽 표면과 비교하여 들어 올려져 있을때에 제거되는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  14. 제10항에 있어서, 상기 형성 단계의 결과, 돌출부 및 홈부가 적층판의 양면에 형성되는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  15. 제10항에 있어서, 상기 도전층은 연질의 유전층에 접착제에 의해서 접착되어, 상기 접착제가 형성 단 계시에는 변위해서 비평면 형상의 패턴 형성을 가능하게 하고, 또한 층 사이에 형성되는 간극을 충전하는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  16. 제1항에 있어서, 제2의 도전성 재료를 유전 재료의 패스로부터 떨어진 위치에 고착시키는 단계를 포함하는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  17. 제16항에 있어서, 상기 도전성 재료가 스프링재인 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  18. 제2항에 있어서, 상기 형성 단계는 시트를 적절한 윤곽 표면으로부터 들어올리는 것으로 달성되어 시트가 이와 같이 들어올려져 있는 사이에 유전 재료가 시트에 겹쳐지는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  19. 제16항에 있어서, 상기 유전 재료에 창부를 뚫고, 도체 패스와 도전성 재료를 창부를 통해서 함께 저온 압력 융해시키는 융해 단계를 포함하는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  20. 제19항에 있어서, 상기 융해 단계는, 응력 경화하여, 접착제로 충전된 힘집중부를 상기 도전성 재료 및 도전 패스중 하나에 설치하는 설치 단계 및 상기 집중부를 이용하여 시트를 유전체 창부에서 저온 압력 융해시키고, 상기 전도성 재료 및 도전 패스의 어셈블리를 적층하는 적층 단계를 포함하는 것을 특징으로 하는 도체 네트워크를 제조하는 방법.
  21. 제3항에 있어서, 상기 시트의 일부를 금속 시트의 제2면으로부터 제거함으로서, 전기적으로 절연되고, 凹부로 된 도체 패스를 형성하는 형성 단계 및 상기 도체 패스의 적어도 한개를 차단함으로서, 일정량의 납땜을 수납하기 위해 한개의 패스중 적어도 한개의 패드부를 절연하는 절연 단계를 포함하는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  22. 제3항에 있어서, 상기 제거 단계는 상기 시트 및 유전 재료가 동일 평면상으로 될때까지, 또한, 상기 도전성 재료가 평면 형상을 갖을 때까지 시트를 제거하는 단계를 포함하는 것을 특징으로 하는 기판상에 도체 네트워크를 제조하는 방법.
  23. 유전층과,상기 유전층에 지지된 도전층을 포함하고, 상기 유전층으로부터 서로 절연된 도체 패스가 형성되며, 또한, 상기 도체 네트워크가 접촉 부재의 도전성 접촉에 정합하는 것을 돕도록 도체 패스가 바깥측으로 경사진 측벽을 갖는 자기 정합성의 도체 패스를 포함하는 것을 특징으로 하는 기판상의 도체 네트워크.
  24. 제23항에 있어서, 상기 도체 패스는 그 집중부에서 대략 3.8밀리미터(0.150인치) 미만 떨어져 있는 것을 특징으로 하는 기판상의 도체 네트워크.
  25. 제23항에 있어서, 상기 도전층의 도체 패스에 압력 융해시켜서 그 사이의 전기적 접속을 얻기 위해 적어도 하나의 노출한 도체 패스를 갖는 제2의 평면 형성 도전층과, 상기 제2의 평면 형상 도체 회로를 각 압력 융해 접속점을 제외한 곳에서 상기 도전층으로부터 절연하기 위한 수단을 포함하는 것을 특징으로 하는 기판상의 도체 네트워크.
  26. 제23항에 있어서, 일정량의 납땜을 수용하도록, 한개의 패스에 대한 한개의 패드부를 절연하기 위해서 상기 도체 패스중 적어도 하나를 차단하기 위한 수단을 포함하는 것을 특징으로 하는 기판상의 도체 네트워크 제조방법.
  27. 평면 형상의 도전성 시트로부터, 상기 시트의 제1면에 유전 재료를 고착시킨 비평면 형상의 패턴을 형성하는 수단 및 상기 시트의 일부를 시트의 제2면으로부터 제거하여 절연된 도체패스를 형성하는 수단을 포함하는 것을 특징으로 하는 연질 도체 네트워크 제조 장치.
  28. 제26항에 있어서, 접착제에 의해 상기 유전 재료를 상기 도전층에 고착시켜, 상기 유전층과 도전층시트 사이를 접착제로 채우기 위한 수단을 포함하는 것을 특징으로 하는 연질 도체 네트워크 제조 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940702819A 1992-02-14 1993-02-10 고밀도 도체 네트워크 및 그 제조방법과 제조장치(High density conductive networks and method and apparatus for making same) KR950700676A (ko)

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US07837357 US5343616B1 (en) 1992-02-14 1992-02-14 Method of making high density self-aligning conductive networks and contact clusters
US837,357 1992-02-14
PCT/US1993/001454 WO1993016574A1 (en) 1992-02-14 1993-02-10 High density conductive networks and method and apparatus for making same

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EP0626124A4 (en) 1995-11-15
US5526565A (en) 1996-06-18
WO1993016574A1 (en) 1993-08-19
CA2128210A1 (en) 1993-08-19
RU94040379A (ru) 1996-08-10
WO1993016575A1 (en) 1993-08-19
JPH07506218A (ja) 1995-07-06
RU2138930C1 (ru) 1999-09-27
US5477612A (en) 1995-12-26
KR100298010B1 (ko) 2001-11-22
US5343616A (en) 1994-09-06
US5343616B1 (en) 1998-12-29
EP0626124A1 (en) 1994-11-30

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