KR950001486A - 플레쉬 메모리 어레이 시스템 및 방법 - Google Patents

플레쉬 메모리 어레이 시스템 및 방법 Download PDF

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KR950001486A
KR950001486A KR1019940013909A KR19940013909A KR950001486A KR 950001486 A KR950001486 A KR 950001486A KR 1019940013909 A KR1019940013909 A KR 1019940013909A KR 19940013909 A KR19940013909 A KR 19940013909A KR 950001486 A KR950001486 A KR 950001486A
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South Korea
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array
executed
user interface
flash memory
array controller
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KR1019940013909A
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KR100276162B1 (ko
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리 팬드리히 미키
조셉 두란트 리챠드
프레드릭 언더우드 키드
알.로즈만 로드니
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칼 실버맨
인텔 코오퍼레이션
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
    • G06F9/45508—Runtime interpretation or emulation, e g. emulator loops, bytecode interpretation
    • G06F9/45512—Command shells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

Abstract

플래쉬 메모리 시스템은 유져 인터페이스와 어레이 제어기를 포함한다. 유져 인터페이스는 프로세서에 의해서 나온 유져 명령을 수신하며 실행을 위한 다수의 명령을 큐잉하는 능력을 갖는다.
유져 인터페이스는 실행될 명령의 우선순위를 제어하기 위해 아비터로서 더욱 기능한다. 어레이 제어기는 프로그램과 소거와 같은 플레쉬 어레이상에서의 동작을 수행한다. 어레이 제어기는 유져에 의해서 프로그램 가능한 프로그램 메모리를 갖는 범용의 프로세서로 이루어진다. 프로그램 메모리는 어레이 제어기에 의해서 실행될 수 있는 하나 또는 그 이상의 알고리즘을 저장한다. 알고리즘은 유져 인터페이스에서 수신된 명령에 따라 선택된다. 알고리즘은 프로그램 메모리를 프로그램함으로써 간단히 주문화될수 있다. 시스템은 높은 우선순위 명령 그러나 현재 실행하고 있는 명령의 문맥스위치를 낮은 우선순위로 수행할 수 있게 하기 위해서 플레쉬 메모리 시스템을 인에이블하는 인터럽트 메카리즘을 제공한다.

Description

플레쉬 메모리 어레이 시스템 및 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 플레쉬 메모리 시스템을 나타내는 블록도, 제3도는 본 발명의 유져 인터페이스(user interface)를 나타내는 블록도, 제4a도는 본 발명의 시스템에서 수신되는 명령코드와 구현되는 어레이 제어기 벡터를 설명하는 테이블.

Claims (2)

  1. 버스를 통해 메모리와 결합된 프로세서로 구성되는 시스템에 있어서, 플레쉬 메모리에 의해서 실행될 명령을 수신하며, 현재 실행하고 있는 명령을 포함하는 하나 또는 그 이상의 명령을 저장하기 위한 명령큐로 구성하는 유져 인터페이스; 실행할 명령을 수신하기 위해 유져 인터페이스와 결합하며, 어레이를 판독, 소거 및 프로그램 하기 위해서 전원을 제어하는 어레이 제어기; 어레이 제어기의 상태를 저장하기 위해 어레이 제어기와 결합된 다수의 레지스터; 및 세트될 때 명령을 실행동안 인터럽트의 발생을 허용하는 인터럽트 상태 비트로 구성되며, 만약 인터럽트 상태 비트가 세트되고 명령큐가 실행하고 있는 현재 명령과 실행될 다음 명령으로 구성된다면, 상기 유져 인터페이스는 인터럽트를 어레이 제어기에 내며, 상기 어레이 제어기는 어레이를 사전 설정된 상태에 두며, 어레이 제어기의 상태를 저장하며 다음 명령을 실행하며, 레지스터에 저장된 상태를 재저장하며, 현재 명령의 실행을 계속하여 그결과 인터럽트가 플레쉬 어레이의 붕괴없이 플레쉬 메모리 시스템에 의해서 처리될 수 있는 것을 특징으로 하는 버스와 결합된 플레쉬 메모리 어레이 시스템.
  2. 제1버스를 통해 메모리와 결합된 프로세서로 구성되는 시스템에 있어서, 데이타 저장을 위한 다수의 플레쉬 셀로 구성되는 플레쉬 어레이; 플레쉬 메모리 시스템에 의해서 실행될 명령을 수신하며, 현재 실행하고 있는 명령을 포함하는 하나 또는 그 이상의 명령을 저장하기 위한 명령큐로 구성되며; 실행될 때 명령을 수행하는 코드의 위치를 식별하는 명령어드레스를 발생시키는 유져 인터페이스; 및 명령어드레스를 수신하기 위해 유져 인터페이스와 결합되고 마이크로 제어기와 프로그램 메모리로 구성되는 어레이 제어기로 구성되며, 상기 프로그램 메모리는 유져에 의해서 프로그램 가능하며, 상기 명령어드레스는 마이크로 제어기가 생행하고자 하는 프로그램 메모리의 코드위치를 식별하며, 상기 마이크로 제어기는 프로그램 메모리의 코드와 일치하여 플레쉬 어레이상에서 기록 및 소거 동작을 수행하며, 여기서, 플레쉬 메모리 시스템은 플레쉬 메모리 시스템의 유연성을 증가시키고 프로세스로부터 플레쉬 어레이의 제어를 오프 로드하여 마이크로 제어기에 의해서 수행될 다수의 기능을 수행하고자 프로그램될 수 있게 되는 것을 특징으로 하는 버스와 결합된 플레쉬 메모리 어레이 시스템.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940013909A 1993-06-30 1994-06-20 플레쉬 메모리 어레이 시스템 및 방법 KR100276162B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/086,186 US5509134A (en) 1993-06-30 1993-06-30 Method and apparatus for execution of operations in a flash memory array
US086,186 1993-06-30

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KR950001486A true KR950001486A (ko) 1995-01-03
KR100276162B1 KR100276162B1 (ko) 2000-12-15

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