KR940027145A - 다층 리드 프레임 - Google Patents

다층 리드 프레임 Download PDF

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Publication number
KR940027145A
KR940027145A KR1019940011157A KR19940011157A KR940027145A KR 940027145 A KR940027145 A KR 940027145A KR 1019940011157 A KR1019940011157 A KR 1019940011157A KR 19940011157 A KR19940011157 A KR 19940011157A KR 940027145 A KR940027145 A KR 940027145A
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KR
South Korea
Prior art keywords
lead frame
ceramic plate
layer
power supply
multilayer lead
Prior art date
Application number
KR1019940011157A
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English (en)
Other versions
KR0125116B1 (ko
Inventor
또시까즈 따게노우찌
뀨니유끼 호리
미쓰하루 시미즈
Original Assignee
이노우에 사다오
신꼬오 덴기 고오교오 가부시끼가이샤
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Publication of KR940027145A publication Critical patent/KR940027145A/ko
Application granted granted Critical
Publication of KR0125116B1 publication Critical patent/KR0125116B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

[목적]
10nF 이상의 큰 정전용량을 달성할 수 있다.
[구성]
적어도 신호층(12), 전원층(14), 접지층(20)을 절연체를 통하여 적층해서 된 다층리드프레임에 있어서 전원층(14)와 접지층(20)사이에 강 유전체로 된 세라믹판(22)을 개장하고, 이 세라믹판(22)과 전원층(14), 접지층(20)사이를 도전성의 접착재(24)로 고착한 것을 특징으로 한다.

Description

다층 리드 프레임
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 제1의 실시예를 나타낸 단면도, 제2도는 세라믹판의 정면도, 제3도는 세라믹판의 양면에 금속피막을 형성한 실시예를 나타낸 부분단면도, 제4또는 클록주파수와 정전용량과의 관계를 나타낸 그래프.

Claims (4)

  1. 적어도 신호층, 전원층, 접지층을 절연체를 통하여 적층해서 된 다층리드프레임에 있어서, 상기 전원층과 접지층 사이에 강 유전체로 된 세라믹판을 개장하고, 이 세라믹판과 상기전원층, 접지층 사이를 도전성의 접착재로 고착한 것을 특징으로 하는 다층리드프레임.
  2. 제1항에 있어서, 상기 세라믹판이 티탄산 바륨 혹은 티타산스트론튬을 주성분으로 하는 세라믹판인 것을 특징으로 하는 다층리드프레임.
  3. 제1항 또는 제2항에 있어서, 상기 도전성의 접착재가 접착성을 갖는 수지 속에 금속 분말을 혼입한 도전성 필림인 것을 특징으로 하는 다층리드프레임.
  4. 제1항 또는 제2항에 있어서, 세라믹판의 양표면에 금속피막이 형성되어 있는 것을 특징으로 하는 다층리드 프레임.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940011157A 1993-05-24 1994-05-23 다층 리드 프레임 KR0125116B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5121328A JPH06334105A (ja) 1993-05-24 1993-05-24 多層リードフレーム
JP93-121328 1993-05-24

Publications (2)

Publication Number Publication Date
KR940027145A true KR940027145A (ko) 1994-12-10
KR0125116B1 KR0125116B1 (ko) 1997-12-11

Family

ID=14808539

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940011157A KR0125116B1 (ko) 1993-05-24 1994-05-23 다층 리드 프레임

Country Status (5)

Country Link
US (1) US5576577A (ko)
EP (1) EP0626725B1 (ko)
JP (1) JPH06334105A (ko)
KR (1) KR0125116B1 (ko)
DE (1) DE69416341T2 (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6066514A (en) 1996-10-18 2000-05-23 Micron Technology, Inc. Adhesion enhanced semiconductor die for mold compound packaging
US5583372A (en) * 1994-09-14 1996-12-10 Micron Technology, Inc. Adhesion enhanced semiconductor die for mold compound packaging
KR0177744B1 (ko) * 1995-08-14 1999-03-20 김광호 전기적 특성이 향상된 반도체 장치
SG60099A1 (en) 1996-08-16 1999-02-22 Sony Corp Semiconductor package and manufacturing method of lead frame
KR100218368B1 (ko) * 1997-04-18 1999-09-01 구본준 리드프레임과 그를 이용한 반도체 패키지 및 그의 제조방법
FR2764115B1 (fr) * 1997-06-02 2001-06-08 Sgs Thomson Microelectronics Dispositif semiconducteur et procede de connexion des fils internes de masse d'un tel dispositif
US6878572B2 (en) * 2002-05-30 2005-04-12 Intel Corporation High capacitance package substrate
JP3943096B2 (ja) * 2004-03-31 2007-07-11 シャープ株式会社 半導体装置、及びその電気的検査方法、並びにそれを備えた電子機器
TWI246760B (en) * 2004-12-22 2006-01-01 Siliconware Precision Industries Co Ltd Heat dissipating semiconductor package and fabrication method thereof
CN101627450B (zh) * 2007-03-08 2013-10-30 日本电气株式会社 电容元件、印刷布线板、半导体封装以及半导体电路
US9484320B2 (en) * 2012-04-27 2016-11-01 Freescale Semiconductor, Inc. Vertically packaged integrated circuit

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JPS5332233B1 (ko) * 1968-12-25 1978-09-07
JPS61108160A (ja) * 1984-11-01 1986-05-26 Nec Corp コンデンサ内蔵型半導体装置及びその製造方法
BE904407A (fr) * 1985-03-13 1986-06-30 Rogers Corp Condensateur de decouplage et methode de fabrication de celui-ci.
US5089878A (en) * 1989-06-09 1992-02-18 Lee Jaesup N Low impedance packaging
US5237202A (en) * 1989-10-16 1993-08-17 Shinko Electric Industries Co., Ltd Lead frame and semiconductor device using same
JP2784235B2 (ja) * 1989-10-16 1998-08-06 新光電気工業株式会社 リードフレーム及び半導体装置
JP2828326B2 (ja) * 1990-07-12 1998-11-25 新光電気工業株式会社 多層リードフレームおよびその製造方法
JPH0479264A (ja) * 1990-07-20 1992-03-12 Nec Corp Ｌｓｉパッケージ
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Also Published As

Publication number Publication date
JPH06334105A (ja) 1994-12-02
DE69416341T2 (de) 1999-07-01
EP0626725B1 (en) 1999-02-03
US5576577A (en) 1996-11-19
EP0626725A2 (en) 1994-11-30
KR0125116B1 (ko) 1997-12-11
DE69416341D1 (de) 1999-03-18
EP0626725A3 (en) 1995-04-19

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