KR940022737A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR940022737A
KR940022737A KR1019940006356A KR19940006356A KR940022737A KR 940022737 A KR940022737 A KR 940022737A KR 1019940006356 A KR1019940006356 A KR 1019940006356A KR 19940006356 A KR19940006356 A KR 19940006356A KR 940022737 A KR940022737 A KR 940022737A
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KR
South Korea
Prior art keywords
oxide film
silicon oxide
fluorine
silicon
stopper
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KR1019940006356A
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English (en)
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KR0127259B1 (ko
Inventor
마사코 고데라
아츠시 시게타
히로유키 야노
Original Assignee
사토 후미오
가부시키가이샤 도시바
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Publication of KR940022737A publication Critical patent/KR940022737A/ko
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Publication of KR0127259B1 publication Critical patent/KR0127259B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 불소를 함유하는 산화규소막을 스톱퍼로 한 폴리싱기술에 의해 절대적으로 평탄화된다.
실리콘기판(21)의 표면상에 제1배선 내지 제4배선 22∼25를 설치하고 이들 배선 22∼25 및 실리콘기판(21)의 위에 불소를 함유하는 산화규소막(26)을 설치하고 상기 불소를 함유하는 산화규소막(26)의 위에 불소를 함유하지 않은 산화규소막(27)을 설치한다. 다음에, 불소를 함유하지 않은 산화규소막(27)을 소정시간 폴리싱하는 것에 의해 평탄화한다. 이 경우, 불소를 함유하는 산화규소막(26)은 불소를 함유하지 않은 산화규소막(27)에 비해서 폴리싱속도가 늦기 때문에 상기 산화규소막(27)의 표면을 연마하는 경우에 상기 산화규소막(26)은 스톱퍼의 역할을 달성한다. 따라서, 상기 산화규소막(27)을 절대적으로 평탄화할 수 있다.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예에 의한 반도체장치의 제조방법을 나타낸 단면도.
제2도는 본 발명의 실시예에 의한 반도체장치의 제조방법을 나타낸 것이며 제1도의 다음 공정을 나타낸 단면도.
제3도는 각종 산화규소막의 폴리싱속도를 나타낸 도면.

Claims (1)

  1. 요철(凹凸)부를 갖는 반도체기판 표면에 불소를 함유하는 산화규소막을 퇴적하는 공정과, 상기 불소를 함유하는 산화규소막의 위에 불소를 함유하지 않은 산화규소막을 퇴적하는 공정 및, 상기 불소를 함유하는 산화규소막을 스톱퍼로 이용하여 상기 불소를 함유하지 않은 산화규소막을 폴리싱함으로써 상기 요철부를 갖춘 반도체기판 표면을 평탄화하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940006356A 1993-03-29 1994-03-29 반도체장치의 제조방법 KR0127259B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP93-69683 1993-03-29
JP06968393A JP3152788B2 (ja) 1993-03-29 1993-03-29 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
KR940022737A true KR940022737A (ko) 1994-10-21
KR0127259B1 KR0127259B1 (ko) 1998-04-02

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KR1019940006356A KR0127259B1 (ko) 1993-03-29 1994-03-29 반도체장치의 제조방법

Country Status (3)

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US (1) US5578531A (ko)
JP (1) JP3152788B2 (ko)
KR (1) KR0127259B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557577B1 (ko) * 2002-12-07 2006-03-03 주식회사 하이닉스반도체 반도체소자의 형성 방법

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0134108B1 (ko) * 1994-06-30 1998-04-20 김주용 반도체 소자의 제조방법
US6127629A (en) * 1994-10-03 2000-10-03 Ford Global Technologies, Inc. Hermetically sealed microelectronic device and method of forming same
JPH09129727A (ja) * 1995-10-30 1997-05-16 Nec Corp 半導体装置及びその製造方法
JP2917897B2 (ja) * 1996-03-29 1999-07-12 日本電気株式会社 半導体装置の製造方法
US6157083A (en) * 1996-06-03 2000-12-05 Nec Corporation Fluorine doping concentrations in a multi-structure semiconductor device
US5763021A (en) * 1996-12-13 1998-06-09 Cypress Semiconductor Corporation Method of forming a dielectric film
KR100399903B1 (ko) * 1996-12-30 2003-12-24 주식회사 하이닉스반도체 반도체 소자 제조시의 층간 평탄화방법
US6048803A (en) * 1997-08-19 2000-04-11 Advanced Microdevices, Inc. Method of fabricating a semiconductor device having fluorine bearing oxide between conductive lines
KR100419878B1 (ko) * 1997-12-11 2004-05-20 주식회사 하이닉스반도체 반도체소자의제조방법
JP3132557B2 (ja) * 1998-04-03 2001-02-05 日本電気株式会社 半導体装置の製造方法
US6383404B1 (en) * 1998-08-19 2002-05-07 Hoya Corporation Glass substrate for magnetic recording medium, magnetic recording medium, and method of manufacturing the same
US6274933B1 (en) * 1999-01-26 2001-08-14 Agere Systems Guardian Corp. Integrated circuit device having a planar interlevel dielectric layer
TW482932B (en) * 1999-07-05 2002-04-11 Matsushita Electric Ind Co Ltd Chemical adsorbate compound, organic film, liquid crystal alignment film, and liquid crystal display device utilizing the chemical adsorbate compound
CN102820256A (zh) * 2011-06-08 2012-12-12 无锡华润上华半导体有限公司 一种金属间介质层的制备方法
CN103094194B (zh) * 2011-11-01 2016-01-13 无锡华润上华科技有限公司 金属层间介质的形成方法及金属层间介质结构

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4652334A (en) * 1986-03-06 1987-03-24 General Motors Corporation Method for patterning silicon dioxide with high resolution in three dimensions
US5106770A (en) * 1990-11-16 1992-04-21 Gte Laboratories Incorporated Method of manufacturing semiconductor devices
JP2697315B2 (ja) * 1991-01-23 1998-01-14 日本電気株式会社 フッ素含有シリコン酸化膜の形成方法
US5169491A (en) * 1991-07-29 1992-12-08 Micron Technology, Inc. Method of etching SiO2 dielectric layers using chemical mechanical polishing techniques
JPH05226480A (ja) * 1991-12-04 1993-09-03 Nec Corp 半導体装置の製造方法
US5302551A (en) * 1992-05-11 1994-04-12 National Semiconductor Corporation Method for planarizing the surface of an integrated circuit over a metal interconnect layer
US5272117A (en) * 1992-12-07 1993-12-21 Motorola, Inc. Method for planarizing a layer of material

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557577B1 (ko) * 2002-12-07 2006-03-03 주식회사 하이닉스반도체 반도체소자의 형성 방법

Also Published As

Publication number Publication date
JP3152788B2 (ja) 2001-04-03
JPH06283485A (ja) 1994-10-07
US5578531A (en) 1996-11-26
KR0127259B1 (ko) 1998-04-02

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