KR940012551A - 와이어 본딩 크랙 방지용 반도체 칩 - Google Patents

와이어 본딩 크랙 방지용 반도체 칩 Download PDF

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Publication number
KR940012551A
KR940012551A KR1019920020407A KR920020407A KR940012551A KR 940012551 A KR940012551 A KR 940012551A KR 1019920020407 A KR1019920020407 A KR 1019920020407A KR 920020407 A KR920020407 A KR 920020407A KR 940012551 A KR940012551 A KR 940012551A
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KR
South Korea
Prior art keywords
wire bonding
semiconductor chip
chip
bonding crack
crack prevention
Prior art date
Application number
KR1019920020407A
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English (en)
Other versions
KR960005043B1 (ko
Inventor
노길섭
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920020407A priority Critical patent/KR960005043B1/ko
Publication of KR940012551A publication Critical patent/KR940012551A/ko
Application granted granted Critical
Publication of KR960005043B1 publication Critical patent/KR960005043B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 패키지 제조용 칩을 리드프레임에 어태치하고 와이어본딩 할 때 와이어본딩에 따른 칩의 본딩 패드크랙을 예방하도록 칩에 관한 것으로, 칩의 Al-Si본딩패드를 라운드형의 Si입자를 사용한 것이며, 와이어 본딩시 본딩패드에 충격이 가해져도 Si입자가 라운드 형태이므로 산화막등의 크랙을 막을 수 있다.

Description

와이어 본딩 크랙 방지용 반도체 칩
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 (가), (나)는 본 발명의 칩패드용 Si입자의 확대 예시도.
제6도는 본 발명의 칩패드 부분확대 단면도이다.

Claims (2)

  1. 반도체 칩을 구성함에 있어서, 칩의 Al-Si본딩패드를 이루는 Si입자로 라운드형 Si입자를 사용함을 특징으로 하는 와이어본딩 크랙방지용 반도체 칩.
  2. 제1항에 있어서, 라운드형 Si입자는 실리콘 모디파이어로 도포된 것을 포함하여 이루어짐을 특징으로 하는 와이어본딩 크랙방지용 반도체 칩.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920020407A 1992-11-02 1992-11-02 와이어 본딩 크랙 방지용 반도체 칩 KR960005043B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920020407A KR960005043B1 (ko) 1992-11-02 1992-11-02 와이어 본딩 크랙 방지용 반도체 칩

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920020407A KR960005043B1 (ko) 1992-11-02 1992-11-02 와이어 본딩 크랙 방지용 반도체 칩

Publications (2)

Publication Number Publication Date
KR940012551A true KR940012551A (ko) 1994-06-23
KR960005043B1 KR960005043B1 (ko) 1996-04-18

Family

ID=19342312

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920020407A KR960005043B1 (ko) 1992-11-02 1992-11-02 와이어 본딩 크랙 방지용 반도체 칩

Country Status (1)

Country Link
KR (1) KR960005043B1 (ko)

Also Published As

Publication number Publication date
KR960005043B1 (ko) 1996-04-18

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