KR940012551A - Semiconductor chip for wire bonding crack prevention - Google Patents
Semiconductor chip for wire bonding crack prevention Download PDFInfo
- Publication number
- KR940012551A KR940012551A KR1019920020407A KR920020407A KR940012551A KR 940012551 A KR940012551 A KR 940012551A KR 1019920020407 A KR1019920020407 A KR 1019920020407A KR 920020407 A KR920020407 A KR 920020407A KR 940012551 A KR940012551 A KR 940012551A
- Authority
- KR
- South Korea
- Prior art keywords
- wire bonding
- semiconductor chip
- chip
- bonding crack
- crack prevention
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract 5
- 230000002265 prevention Effects 0.000 title 1
- 239000011856 silicon-based particle Substances 0.000 claims abstract 4
- 229910018125 Al-Si Inorganic materials 0.000 claims abstract 2
- 229910018520 Al—Si Inorganic materials 0.000 claims abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 238000010276 construction Methods 0.000 claims 1
- 239000003607 modifier Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 반도체 패키지 제조용 칩을 리드프레임에 어태치하고 와이어본딩 할 때 와이어본딩에 따른 칩의 본딩 패드크랙을 예방하도록 칩에 관한 것으로, 칩의 Al-Si본딩패드를 라운드형의 Si입자를 사용한 것이며, 와이어 본딩시 본딩패드에 충격이 가해져도 Si입자가 라운드 형태이므로 산화막등의 크랙을 막을 수 있다.The present invention relates to a chip to prevent the bonding pad crack of the chip due to wire bonding when attaching the chip for the semiconductor package manufacturing to the lead frame and wire bonding, using the Si-type Al-Si bonding pad of the chip Even when an impact is applied to the bonding pad at the time of wire bonding, since the Si particles are rounded, cracks such as an oxide film can be prevented.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제5도는 (가), (나)는 본 발명의 칩패드용 Si입자의 확대 예시도.Figure 5 is (a), (b) is an enlarged illustration of the Si pad for chip pad of the present invention.
제6도는 본 발명의 칩패드 부분확대 단면도이다.6 is an enlarged cross-sectional view of the chip pad of the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920020407A KR960005043B1 (en) | 1992-11-02 | 1992-11-02 | Semiconductor chip for preventing wire-bonding crack |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920020407A KR960005043B1 (en) | 1992-11-02 | 1992-11-02 | Semiconductor chip for preventing wire-bonding crack |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940012551A true KR940012551A (en) | 1994-06-23 |
KR960005043B1 KR960005043B1 (en) | 1996-04-18 |
Family
ID=19342312
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920020407A KR960005043B1 (en) | 1992-11-02 | 1992-11-02 | Semiconductor chip for preventing wire-bonding crack |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960005043B1 (en) |
-
1992
- 1992-11-02 KR KR1019920020407A patent/KR960005043B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR960005043B1 (en) | 1996-04-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20090406 Year of fee payment: 14 |
|
LAPS | Lapse due to unpaid annual fee |