KR940012586A - Multilayer ceramic package - Google Patents

Multilayer ceramic package Download PDF

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Publication number
KR940012586A
KR940012586A KR1019920022699A KR920022699A KR940012586A KR 940012586 A KR940012586 A KR 940012586A KR 1019920022699 A KR1019920022699 A KR 1019920022699A KR 920022699 A KR920022699 A KR 920022699A KR 940012586 A KR940012586 A KR 940012586A
Authority
KR
South Korea
Prior art keywords
layer
multilayer ceramic
ceramic package
package
bonding
Prior art date
Application number
KR1019920022699A
Other languages
Korean (ko)
Other versions
KR100237669B1 (en
Inventor
심성민
김영대
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920022699A priority Critical patent/KR100237669B1/en
Publication of KR940012586A publication Critical patent/KR940012586A/en
Application granted granted Critical
Publication of KR100237669B1 publication Critical patent/KR100237669B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

반도체 칩과 다층 세라믹 패키지의 결합을 위해서 칩 그리고 메탈리드와 와이어 또는 열압착으로 연결되는 패키지의 금속화층은 세라믹 기판(1)위에 텅스텐 (W)층과, 그 위에 TiN층과, 그 위에 Au층의 다층으로 구성되며, Au층은 외부와 연결되며 열공정시 상기 Ti가 Au 표면으로 확산되지 않도록 한 것을 특징으로 하는 다층 세라믹 패키지.For the bonding of semiconductor chips and multilayer ceramic packages, the metallization layer of the chip and the package which is connected by metal lead and wire or thermocompression bonding is a tungsten (W) layer on the ceramic substrate (1), a TiN layer on it, and an Au layer thereon. The multilayer ceramic package, characterized in that the Au layer is connected to the outside and the Ti is not diffused to the Au surface during the thermal process.

Description

다층 세라믹 패키지Multilayer ceramic package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 다층 세라믹 패키지 (MLP)의 사시도.1 is a perspective view of a multilayer ceramic package (MLP).

제2도는 MLP의 부분적으로 단면이 도시된 측면도.2 is a side view showing a partial cross section of the MLP.

제3도 (a), (b)는 본 발명에 따라서 제2도의 A 부분인 금속화층의 구조에 대한 단면도이다.3 (a) and 3 (b) are sectional views of the structure of the metallization layer which is part A of FIG. 2 according to the present invention.

Claims (3)

반도체 칩과 다층 세라믹 패키지의 결합을 위해서 칩 그리고 메탈리드와 와이어 또는 열압착으로 연결되는 패키지의 금속화층은 세라믹 기판(1)위에 텅스텐 (W)층과, 그 위에 TiN층과, 그 위에 Au층의 다층으로 구성되며, Au층은 외부와 연결되며 열공정시 상기 Ti와 Au표면으로 확산되지 않도록 한 것을 특징으로 하는 다층 세라믹 패키지.For the bonding of semiconductor chips and multilayer ceramic packages, the metallization layer of the chip and the package which is connected by metal lead and wire or thermocompression bonding is a tungsten (W) layer on the ceramic substrate (1), a TiN layer on it, and an Au layer thereon. The multilayer ceramic package, characterized in that the Au layer is connected to the outside and is not diffused to the Ti and Au surface during the thermal process. 제1항에 있어서, 상기 W층과 TiN층간에에 Ni층을 더욱 포함하도록 구성됨을 특징으로 하는 다층 세라믹 패키지.The multilayer ceramic package of claim 1, further comprising a Ni layer between the W layer and the TiN layer. 제1항에 있어서, 상기 Au층과 W층상의 Ni위에 O2플라즈마 처리로 Ni 산화층을 형성시킴을 특징으로 하는 다층 세라믹 패키지.The multilayer ceramic package according to claim 1, wherein a Ni oxide layer is formed on the Au layer and the Ni layer on the Ni layer by O 2 plasma treatment. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920022699A 1992-11-28 1992-11-28 Multi layer ceramic package KR100237669B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920022699A KR100237669B1 (en) 1992-11-28 1992-11-28 Multi layer ceramic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920022699A KR100237669B1 (en) 1992-11-28 1992-11-28 Multi layer ceramic package

Publications (2)

Publication Number Publication Date
KR940012586A true KR940012586A (en) 1994-06-23
KR100237669B1 KR100237669B1 (en) 2000-01-15

Family

ID=19344191

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920022699A KR100237669B1 (en) 1992-11-28 1992-11-28 Multi layer ceramic package

Country Status (1)

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KR (1) KR100237669B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100112425A (en) * 2009-04-09 2010-10-19 (주)와이에스썸텍 The method for forming high heat sink insulation layer of metal substrates and metal substrates produced by using the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2571944B2 (en) * 1987-11-25 1997-01-16 京セラ株式会社 Chip carrier
JPH0311653A (en) * 1989-06-07 1991-01-18 Nec Yamagata Ltd Semiconductor device

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Publication number Publication date
KR100237669B1 (en) 2000-01-15

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